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    Clocking of client signals output from an egress node in a network
    1.
    发明授权
    Clocking of client signals output from an egress node in a network 有权
    从网络中的出口节点输出的客户端信号的时钟

    公开(公告)号：US08705402B2

    公开(公告)日：2014-04-22

    申请号：US12647342

    申请日：2009-12-24

    申请人： Tulasi Veguru ,  Gopal Rao ,  Prasad Paranjape ,  Ting-Kuang Chiang ,  Konstantin Saunichev

    发明人： Tulasi Veguru ,  Gopal Rao ,  Prasad Paranjape ,  Ting-Kuang Chiang ,  Konstantin Saunichev

    IPC分类号： H04J3/07 ,  H04L12/50 ,  G06F15/173

    CPC分类号： H04L47/22 ,  H04L47/365

    摘要： Consistent with the present disclosure, client data, which may include multiplexed data sub-streams, is supplied to an ingress node of a network. Each sub-stream typically has a corresponding data rate, i.e., an original data rate, prior to multiplexing. The client data is encapsulated in a plurality of successive frames that are output from the ingress node and propagate, typically through one or more intermediate nodes, to an egress node. At the egress node, data rates associated with the sub-streams included in each frame are determined based on the amount of client data in each frame. The data rates are then averaged over a given number of frames to thereby filter any wander or deviation in the client data rate. Based on the averaged data rate, justification opportunities are added to the client data in each sub-stream, which are then multiplexed into frames that are output from the egress node. By including the justification opportunities, the effective rate of each sub-stream may be set equal to the original data rate when the sub-streams are demultiplexed after being output from the egress node. An advantage of the present disclosure is that the justification opportunities, are not generated based solely on clock signals generated by PLL circuits. As a result, fewer PLL circuits are required, thereby simplifying system design and minimizing power consumption.

    摘要翻译： 根据本公开，可以将包括多路复用数据子流的客户端数据提供给网络的入口节点。 每个子流在复用之前通常具有对应的数据速率，即原始数据速率。 客户端数据被封装在从入口节点输出并且通常通过一个或多个中间节点传播到出口节点的多个连续帧中。 在出口节点处，基于每帧中的客户端数据的量来确定与包括在每个帧中的子流相关联的数据速率。 然后在给定数量的帧上对数据速率进行平均，从而过滤客户端数据速率中的任何漂移或偏差。 基于平均数据速率，将每个子流中的客户端数据加入调整机会，然后将其合并到从出口节点输出的帧中。 通过包括调整机会，在从出口节点输出之后子流被解复用时，每个子流的有效速率可被设置为等于原始数据速率。 本公开的优点在于，调整机会不是仅仅由PLL电路产生的时钟信号产生。 因此，需要更少的PLL电路，从而简化系统设计并最大限度地降低功耗。

    Digital framer architecture with a framing marker
    2.
    发明授权
    Digital framer architecture with a framing marker 有权
    具有框架标记的数字成帧器架构

    公开(公告)号：US08189623B2

    公开(公告)日：2012-05-29

    申请号：US12242922

    申请日：2008-10-01

    申请人： Prasad Paranjape ,  Tom Wellbaum

    发明人： Prasad Paranjape ,  Tom Wellbaum

    IPC分类号： H04J3/06

    CPC分类号： H04J14/0227 ,  H04J3/1611 ,  H04J14/0246 ,  H04J14/0284

    摘要： Embodiments of the present invention provide for diverse routing of a plurality of data streams, representative of a client signal of an unknown format, across multiple communication paths of a digital optical network through the use of a marker embedded in the client signal which is then inserted into the client payload portion of a transport frame. The multiple communication paths include different signal and path attributes related to the optical signals which transport the data streams across the digital optical network, as well as the physical structure of the digital optical network itself, all leading to timing variations in the multiple communication paths. The digital optical network transports the plurality of data streams in the form of wavelength division multiplexed signals, or banded wavelength division multiplexed signals.

    摘要翻译： 本发明的实施例通过使用嵌入在客户端信号中的标记来提供代表数字光网络的多个通信路径的代表未知格式的客户端信号的多个数据流的多样化路由，然后插入该标记 进入传输帧的客户端有效载荷部分。 多个通信路径包括与传输数字光网络上的数据流的光信号以及数字光网络本身的物理结构相关的不同信号和路径属性，这些都导致多个通信路径中的定时变化。 数字光网络以波分复用信号或带状波分复用信号的形式传送多个数据流。

    DIGITAL FRAMER ARCHITECTURE WITH A FRAMING MARKER
    4.
    发明申请
    DIGITAL FRAMER ARCHITECTURE WITH A FRAMING MARKER 有权
    数字框架架构与框架标记

    公开(公告)号：US20100080561A1

    公开(公告)日：2010-04-01

    申请号：US12242922

    申请日：2008-10-01

    申请人： Prasad Paranjape ,  Tom Wellbaum

    发明人： Prasad Paranjape ,  Tom Wellbaum

    IPC分类号： H04J14/02 ,  H04B10/00

    CPC分类号： H04J14/0227 ,  H04J3/1611 ,  H04J14/0246 ,  H04J14/0284

    摘要： Embodiments of the present invention provide for diverse routing of a plurality of data streams, representative of a client signal of an unknown format, across multiple communication paths of a digital optical network through the use of a marker embedded in the client signal which is then inserted into the client payload portion of a transport frame. The multiple communication paths include different signal and path attributes related to the optical signals which transport the data streams across the digital optical network, as well as the physical structure of the digital optical network itself, all leading to timing variations in the multiple communication paths. The digital optical network transports the plurality of data streams in the form of wavelength division multiplexed signals, or banded wavelength division multiplexed signals.

    摘要翻译： 本发明的实施例通过使用嵌入在客户端信号中的标记来提供代表数字光网络的多个通信路径的代表未知格式的客户端信号的多个数据流的多样化路由，然后插入该标记 进入传输帧的客户端有效载荷部分。 多个通信路径包括与传输数字光网络上的数据流的光信号以及数字光网络本身的物理结构相关的不同信号和路径属性，这些都导致多个通信路径中的定时变化。 数字光网络以波分复用信号或带状波分复用信号的形式传送多个数据流。

    Apparatus and method for optimizing an iterative FEC decoder
    7.
    发明授权
    Apparatus and method for optimizing an iterative FEC decoder 有权
    用于优化迭代FEC解码器的装置和方法

    公开(公告)号：US08839066B2

    公开(公告)日：2014-09-16

    申请号：US12728515

    申请日：2010-03-22

    申请人： Prasad Paranjape

    发明人： Prasad Paranjape

    IPC分类号： H03M13/00

    CPC分类号： H03M13/3738 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/3715 ,  H03M13/3746 ,  H03M13/3753 ,  H04L1/005

    摘要： Consistent the present disclosure, errored bits are inserted into a data stream, which is carried by an optical signal. The optical signal is transmitted over an optical link that may induce additional errors, i.e., add additional errored bits to the data stream. At the receive end, the optical signal is converted into a corresponding electrical signal that carries the data stream. The data stream is subject to forward error correction (FEC) decoding with an iterative decoder, for example. The iterative decoder decodes the data stream over a number of iterations until both the inserted errored bits and the additional errored bits are corrected. Since the number of inserted bits is known, the number of iterations required to correct the inserted bits is also known (“first iterations”). Accordingly, the number of iterations required to correct the additional errored bits caused by transmission over the optical link may be determined based on the total number of iterations performed and the number of the first iterations.

    摘要翻译： 与本公开一致，错误比特被插入由光信号承载的数据流中。 光信号通过可能引起附加错误的光链路传输，即向数据流添加额外的错误位。 在接收端，光信号被转换为携带数据流的对应电信号。 数据流例如使用迭代解码器进行前向纠错（FEC）解码。 迭代解码器通过多次迭代解码数据流，直到插入的错误位和附加错误位被校正。 由于插入位的数量是已知的，所以校正插入位所需的迭代次数也是已知的（“第一次迭代”）。 因此，可以基于执行的迭代的总数和第一次迭代的次数来确定校正由光链路上的传输引起的附加错误比特所需的迭代次数。

    Devices for conversion between serial and parallel data
    8.
    发明授权
    Devices for conversion between serial and parallel data 有权
    串行和并行数据之间转换的设备

    公开(公告)号：US08188894B2

    公开(公告)日：2012-05-29

    申请号：US12495482

    申请日：2009-06-30

    申请人： Chung Kuang Chin ,  Prasad Paranjape

    发明人： Chung Kuang Chin ,  Prasad Paranjape

    IPC分类号： H03M9/00

    CPC分类号： H03M9/00 ,  H04J3/047

    摘要： Serial-to-parallel and parallel-to-serial conversion devices may provide for efficient conversion of serial bit streams into parallel data units (and vice versa). In one implementation, a device may include delay circuits, each of which being configured to receive a serial data stream. A rotator circuit may receive the delayed serial data streams and rearrange bits in the serial data streams. Register circuits may receive the output of the rotator circuit and collectively output, in parallel, a number of bits of one of the serial bit streams.

    摘要翻译： 串行到并行和并行到串行转换设备可以提供将串行比特流有效转换成并行数据单元（反之亦然）。 在一个实现中，设备可以包括延迟电路，每个延迟电路被配置为接收串行数据流。 旋转电路可以接收延迟的串行数据流并重新排列串行数据流中的位。 寄存器电路可以接收转子电路的输出并且并行地并行地输出串行位流之一的多个位。

    Temporal alignment of data unit groups in a switch
    10.
    发明授权
    Temporal alignment of data unit groups in a switch 有权
    交换机中数据单元组的时间对齐

    公开(公告)号：US08300479B2

    公开(公告)日：2012-10-30

    申请号：US12731948

    申请日：2010-03-25

    申请人： Chung Kuang Chin ,  Edward E. Sprague ,  Prasad Paranjape ,  Swaroop Raghunatha ,  Venkat Talapaneni

    发明人： Chung Kuang Chin ,  Edward E. Sprague ,  Prasad Paranjape ,  Swaroop Raghunatha ,  Venkat Talapaneni

    IPC分类号： G11C7/00 ,  G11C8/00

    CPC分类号： H04J3/0685 ,  H04J3/062

    摘要： Consistent with the present disclosure, a plurality of FIFO buffers, for example, are provided in a switch, which also includes a switch fabric. Each of the plurality of FIFOs is pre-filled with data for a duration based on a skew or time difference between the time that a data unit group is supplied to its corresponding FIFO and a reference time. The reference time is the time, for example, after a delay period has lapsed following the leading edge of a synch signal, the timing of which is a known system parameter and is used to trigger switching in the switch fabric. Typically, the delay period may be equal to the latency (often, another known system parameter) or length of time required for the data unit to propagate from an input circuit, such as a line card of the switch or another switch, to the FIFO that receives the data unit. At the reference time, temporally aligned data unit groups may be read or output from each FIFO and supplied to the switch fabric. Since the timing of the output from the FIFOs is based on known system parameters, instead of the actual arrival of the slowest data unit group at its corresponding FIFO, time aligned data unit groups may be output regardless of whether the slowest data unit group is available.

    摘要翻译： 与本公开一致，例如在交换机中提供多个FIFO缓冲器，交换机还包括交换结构。 基于在将数据单元组提供给其对应的FIFO的时间与参考时间之间的偏差或时间差，多个FIFO中的每一个被预先填充数据持续一段时间。 参考时间是时间，例如，在同步信号的前沿经过延迟时间之后，其定时是已知的系统参数，并且用于触发交换结构中的切换。 通常，延迟周期可以等于数据单元从诸如交换机或另一交换机的线路卡的输入电路传播到FIFO的等待时间（通常是另一个已知的系统参数）或时间长度 它接收数据单元。 在参考时间，可以从每个FIFO读取或输出时间对齐的数据单元组并提供给交换结构。 由于来自FIFO的输出的定时是基于已知的系统参数，而不是最慢的数据单元组在其对应的FIFO的实际到达，可以输出时间对齐的数据单元组，而不管最慢的数据单元组是否可用 。