DISTRIBUTED MICRO INSTRUCTIONS SET PROCESSOR ARCHITECTURE FOR HIGH-EFFICIENCY SIGNAL PROCESSING
    1.
    发明申请
    DISTRIBUTED MICRO INSTRUCTIONS SET PROCESSOR ARCHITECTURE FOR HIGH-EFFICIENCY SIGNAL PROCESSING 有权
    分布式微指令设置高效信号处理的处理器架构

    公开(公告)号:US20110314257A1

    公开(公告)日:2011-12-22

    申请号:US13194547

    申请日:2011-07-29

    IPC分类号: G06F15/76 G06F9/06

    摘要: A wireless communication system hosts a plurality of processes in accordance with a communication protocol. The system includes application specific instruction set processors (ASISPs) that provided computation support for the process. Each ASISP is capable of executing a subset of the functions of a communication protocol. A scheduler is used to schedule the ASISPs in a time-sliced algorithm so that each ASISP supports several processes. In this architecture, the ASISP actively performs computations for one of the supported processes (active process) at any given time. The state information of each process supported by a particular ASISP is stored in a memory bank that is uniquely associated with the ASISP. When a scheduler instructs an ASISP to change which process is the active process, the state information for the inactivated process is stored in the memory bank and the state information for the newly activated process is retrieved from the memory bank.

    摘要翻译: 无线通信系统根据通信协议承载多个进程。 该系统包括为该过程提供计算支持的特定于应用程序的指令集处理器(ASISP)。 每个ASISP能够执行通信协议的功能的子集。 调度程序用于以时间分片算法调度ASISP,以便每个ASISP支持多个进程。 在这种体系结构中,ASISP在任何给定的时间主动执行一个受支持进程(活动进程)的计算。 由特定ASISP支持的每个进程的状态信息存储在与ASISP唯一相关联的存储体中。 当调度器指示ASISP改变哪个进程是活动进程时,将非活动进程的状态信息存储在存储体中,并且从存储体检索新激活的进程的状态信息。

    Distributed micro instruction set processor architecture for high-efficiency signal processing
    2.
    发明授权
    Distributed micro instruction set processor architecture for high-efficiency signal processing 有权
    分布式微指令集处理器架构,用于高效率信号处理

    公开(公告)号:US08014786B2

    公开(公告)日:2011-09-06

    申请号:US11841604

    申请日:2007-08-20

    IPC分类号: H04Q7/20

    摘要: A wireless communication system hosts a plurality of processes in accordance with a communication protocol. The system includes application specific instruction set processors (ASISPs) that provided computation support for the process. Each ASISP is capable of executing a subset of the functions of a communication protocol. A scheduler is used to schedule the ASISPs in a time-sliced algorithm so that each ASISP supports several processes. In this architecture, the ASISP actively performs computations for one of the supported processes (active process) at any given time. The state information of each process supported by a particular ASISP is stored in a memory bank that is uniquely associated with the ASISP. When a scheduler instructs an ASISP to change which process is the active process, the state information for the inactivated process is stored in the memory bank and the state information for the newly activated process is retrieved from the memory bank.

    摘要翻译: 无线通信系统根据通信协议承载多个进程。 该系统包括为该过程提供计算支持的特定于应用程序的指令集处理器(ASISP)。 每个ASISP能够执行通信协议的功能的子集。 调度程序用于以时间分片算法调度ASISP,以便每个ASISP支持多个进程。 在这种体系结构中,ASISP在任何给定的时间主动执行一个受支持进程(活动进程)的计算。 由特定ASISP支持的每个进程的状态信息存储在与ASISP唯一相关联的存储体中。 当调度器指示ASISP改变哪个进程是活动进程时,将非活动进程的状态信息存储在存储体中,并且从存储体检索新激活的进程的状态信息。

    Configurable code generator system for spread spectrum applications
    4.
    发明授权
    Configurable code generator system for spread spectrum applications 有权
    用于扩频应用的可配置代码生成器系统

    公开(公告)号:US06567017B2

    公开(公告)日:2003-05-20

    申请号:US09751782

    申请日:2000-12-29

    IPC分类号: H03M700

    摘要: A configurable code generator system (CGS) for spread spectrum applications is disclosed herein. The CGS includes a composite code generator unit (CGU), a global code generator, and an interface that is coupled to the composite code generator and the global code generator. The CGU has multiple independent code generators, each capable of generating an independent code sequence. The global code generator provides a global code sequence for synchronization. The interface has memory that stores at least one bit of the global sequence and at least one bit from at least one of the independent code sequences of the CGU from which an output conditioning circuit can selectively choose based on a desired communication protocol.

    摘要翻译: 本文公开了用于扩展频谱应用的可配置代码生成器系统(CGS)。 CGS包括复合代码发生器单元(CGU),全局代码生成器以及耦合到复合代码生成器和全局代码生成器的接口。 CGU具有多个独立的代码生成器,每个代码生成器能够生成独立的代码序列。 全局代码生成器提供用于同步的全局代码序列。 接口具有存储器,其存储全局序列的至少一个比特和来自CGU的至少一个独立码序列的至少一个比特,其中输出调节电路可以根据期望的通信协议从其中选择性地选择。

    Distributed micro instructions set processor architecture for high-efficiency signal processing
    6.
    发明授权
    Distributed micro instructions set processor architecture for high-efficiency signal processing 有权
    分布式微指令集处理器架构,用于高效率信号处理

    公开(公告)号:US08244270B2

    公开(公告)日:2012-08-14

    申请号:US13194547

    申请日:2011-07-29

    IPC分类号: H04Q7/20 H04W72/00

    摘要: A wireless communication system hosts a plurality of processes in accordance with a communication protocol. The system includes application specific instruction set processors (ASISPs) that provided computation support for the process. Each ASISP is capable of executing a subset of the functions of a communication protocol. A scheduler is used to schedule the ASISPs in a time-sliced algorithm so that each ASISP supports several processes. In this architecture, the ASISP actively performs computations for one of the supported processes (active process) at any given time. The state information of each process supported by a particular ASISP is stored in a memory bank that is uniquely associated with the ASISP. When a scheduler instructs an ASISP to change which process is the active process, the state information for the inactivated process is stored in the memory bank and the state information for the newly activated process is retrieved from the memory bank.

    摘要翻译: 无线通信系统根据通信协议承载多个进程。 该系统包括为该过程提供计算支持的特定于应用程序的指令集处理器(ASISP)。 每个ASISP能够执行通信协议的功能的子集。 调度程序用于以时间分片算法调度ASISP,以便每个ASISP支持多个进程。 在这种体系结构中,ASISP在任何给定的时间主动执行一个受支持进程(活动进程)的计算。 由特定ASISP支持的每个进程的状态信息存储在与ASISP唯一相关联的存储体中。 当调度器指示ASISP改变哪个进程是活动进程时,将非活动进程的状态信息存储在存储体中,并且从存储体检索新激活的进程的状态信息。