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    Clock EMI reduction
    1.
    发明申请
    Clock EMI reduction 有权
    时钟EMI降低

    公开(公告)号：US20070103883A1

    公开(公告)日：2007-05-10

    申请号：US11253646

    申请日：2005-10-20

    申请人： Sheng Wu ,  Noah Gottfried ,  James Burnell ,  Corey Dayton

    发明人： Sheng Wu ,  Noah Gottfried ,  James Burnell ,  Corey Dayton

    IPC分类号： H05K9/00

    CPC分类号： H05K9/0066

    摘要： EMI emissions generated by clock signals in a multi-slot electronic system are reduced by providing out-of-phase clock signals to alternate slots, which cause EMI emissions at typical testing distances and farther to be reduced. An electronic equipment comprises a plurality of slots, each slot operable to receive a clock signal and a plurality of phases of the clock signal, wherein a first phase of the clock signal is routed to a portion of the slots and a second phase of the clock signal is routed to a different portion of the slots. The second phase of the clock signal may be substantially 180° out-of-phase with the first phase of the clock signal.

    摘要翻译： 通过向交替的时隙提供异相时钟信号来减少多时隙电子系统中的时钟信号产生的EMI辐射，从而在典型的测试距离上导致EMI发射，并进一步减少。 电子设备包括多个时隙，每个时隙可操作以接收时钟信号和时钟信号的多个相位，其中时钟信号的第一相位被路由到时隙的一部分和时钟的第二相位 信号被路由到时隙的不同部分。 时钟信号的第二相可以与时钟信号的第一相位基本上为180°异相。

    System and method for multiplexing a time-reference signal and a frequency-reference signal
    4.
    发明授权
    System and method for multiplexing a time-reference signal and a frequency-reference signal 有权
    用于复用时间参考信号和频率参考信号的系统和方法

    公开(公告)号：US08457267B2

    公开(公告)日：2013-06-04

    申请号：US12971490

    申请日：2010-12-17

    申请人： Joseph G. Trotta ,  Noah Gottfried ,  Richard Gammenthaler

    发明人： Joseph G. Trotta ,  Noah Gottfried ,  Richard Gammenthaler

    IPC分类号： H04L7/00 ,  H04L7/02 ,  H04L7/033

    CPC分类号： H04L7/0008 ,  H04J3/0614 ,  H04J3/0685 ,  H04L7/02 ,  H04L7/033 ,  H04L7/0331 ,  H04L7/0337

    摘要： A system may include a bus carrying signals, a frame pulse generator generating a generally periodic frame pulse signal having timing boundaries delineating consecutive timing periods and a frame pulse enable signal active for a portion of each timing period proximate to the timing boundaries and inactive otherwise, a first controlled buffer driving the frame pulse signal on the bus during durations in which the frame pulse enable signal is active to generate a modified frame pulse, a reference clock controller receiving the modified frame pulse via the bus and generating a reference clock enable signal in response to presence of the modified frame pulse, a reference clock generator generating a generally periodic reference clock signal, and a second controlled buffer driving the reference clock signal on the bus during durations in which the reference clock enable signal is active to generate a modified reference clock.

    摘要翻译： 系统可以包括承载信号的总线，帧脉冲发生器，其生成具有描绘连续定时周期的定时边界的大致周期性帧脉冲信号，以及对于定时边界附近的每个定时周期的一部分有效的帧脉冲使能信号， 第一控制缓冲器，在帧脉冲使能信号有效以产生修改的帧脉冲的持续时间期间，在总线上驱动帧脉冲信号，参考时钟控制器经由总线接收经修改的帧脉冲，并产生参考时钟使能信号 响应于修改的帧脉冲的存在，产生大致周期性参考时钟信号的参考时钟发生器，以及在参考时钟使能信号有效以产生修改的参考的持续时间期间在总线上驱动参考时钟信号的第二受控缓冲器 时钟。

    SYSTEM AND METHOD FOR MULTIPLEXING A TIME-REFERENCE SIGNAL AND A FREQUENCY-REFERENCE SIGNAL
    5.
    发明申请
    SYSTEM AND METHOD FOR MULTIPLEXING A TIME-REFERENCE SIGNAL AND A FREQUENCY-REFERENCE SIGNAL 有权
    用于多路复用时间参考信号和频率参考信号的系统和方法

    公开(公告)号：US20120155585A1

    公开(公告)日：2012-06-21

    申请号：US12971490

    申请日：2010-12-17

    申请人： Joseph G. Trotta ,  Noah Gottfried ,  Richard Gammenthaler

    发明人： Joseph G. Trotta ,  Noah Gottfried ,  Richard Gammenthaler

    IPC分类号： H04L7/00

    CPC分类号： H04L7/0008 ,  H04J3/0614 ,  H04J3/0685 ,  H04L7/02 ,  H04L7/033 ,  H04L7/0331 ,  H04L7/0337

    摘要： A system may include a bus carrying signals, a frame pulse generator generating a generally periodic frame pulse signal having timing boundaries delineating consecutive timing periods and a frame pulse enable signal active for a portion of each timing period proximate to the timing boundaries and inactive otherwise, a first controlled buffer driving the frame pulse signal on the bus during durations in which the frame pulse enable signal is active to generate a modified frame pulse, a reference clock controller receiving the modified frame pulse via the bus and generating a reference clock enable signal in response to presence of the modified frame pulse, a reference clock generator generating a generally periodic reference clock signal, and a second controlled buffer driving the reference clock signal on the bus during durations in which the reference clock enable signal is active to generate a modified reference clock.

    摘要翻译： 系统可以包括承载信号的总线，帧脉冲发生器，其生成具有描绘连续定时周期的定时边界的大致周期性帧脉冲信号，以及对于定时边界附近的每个定时周期的一部分有效的帧脉冲使能信号， 第一控制缓冲器，在帧脉冲使能信号有效以产生修改的帧脉冲的持续时间期间，在总线上驱动帧脉冲信号，参考时钟控制器经由总线接收经修改的帧脉冲，并产生参考时钟使能信号 响应于修改的帧脉冲的存在，产生大致周期性参考时钟信号的参考时钟发生器，以及在参考时钟使能信号有效以产生修改的参考的持续时间期间在总线上驱动参考时钟信号的第二受控缓冲器 时钟。

    Clock EMI reduction
    6.
    发明授权
    Clock EMI reduction 有权
    时钟EMI降低

    公开(公告)号：US07519120B2

    公开(公告)日：2009-04-14

    申请号：US11253646

    申请日：2005-10-20

    申请人： Sheng Wu ,  Noah Gottfried ,  James Burnell ,  Corey M. Dayton

    发明人： Sheng Wu ,  Noah Gottfried ,  James Burnell ,  Corey M. Dayton

    IPC分类号： H04L27/00 ,  H05K9/00

    CPC分类号： H05K9/0066

    摘要： EMI emissions generated by clock signals in a multi-slot electronic system are reduced by providing out-of-phase clock signals to alternate slots, which cause EMI emissions at typical testing distances and farther to be reduced. An electronic equipment comprises a plurality of slots, each slot operable to receive a clock signal and a plurality of phases of the clock signal, wherein a first phase of the clock signal is routed to a portion of the slots and a second phase of the clock signal is routed to a different portion of the slots. The second phase of the clock signal may be substantially 180° out-of-phase with the first phase of the clock signal.

    摘要翻译： 通过向交替的时隙提供异相时钟信号来减少多时隙电子系统中的时钟信号产生的EMI辐射，从而在典型的测试距离上导致EMI发射，并进一步减少。 电子设备包括多个时隙，每个时隙可操作以接收时钟信号和时钟信号的多个相位，其中时钟信号的第一相位被路由到时隙的一部分和时钟的第二相位 信号被路由到时隙的不同部分。 时钟信号的第二相可以与时钟信号的第一相位基本上为180°异相。