公开(公告)号：US20170249983A1

公开(公告)日：2017-08-31

申请号：US15324319

申请日：2015-06-03

申请人： Ji Hoon Park ,  Husam N. Alshareef ,  Mohd A. Khan ,  Ihab N. Odeh ,  SABIC Global Technologies B.V.

发明人： Ji Hoon Park ,  Husam N. Alshareef ,  Mohd A. Khan ,  Ihab N. Odeh

IPC分类号： G11C11/22 ,  H01L27/11509 ,  G11C11/56

CPC分类号： G11C11/2275 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2277 ,  G11C11/5657 ,  H01L27/11509 ,  H01L27/20

摘要： Ferroelectric components, such as the ferroelectric field effect transistors (FeFETs), ferroelectric capacitors and ferroelectric diodes described above may be operated as multi-level memory cells as described by the present invention. Storing multiple bits of information in each multi-level memory cell may be performed by a controller coupled to an array of the ferroelectric components configured as ferroelectric memory cells. The controller may execute the steps of receiving a bit pattern for writing to a multi-level memory cell comprising a ferroelectric layer; selecting a pulse duration for applying a write pulse to the memory cell based, at least in part, on the received bit pattern; and applying at least one write pulse to the memory cell having the selected pulse duration, in which the at least one write pulse creates a remnant polarization within the ferroelectric layer that is representative of the received bit pattern.