Automatic cache activation and deactivation for power reduction
    4.
    发明申请
    Automatic cache activation and deactivation for power reduction 有权
    自动缓存激活和停用以降低功耗

    公开(公告)号:US20060156048A1

    公开(公告)日:2006-07-13

    申请号:US11034617

    申请日:2005-01-13

    IPC分类号: G06F1/32

    CPC分类号: G06F1/3203 Y02D10/126

    摘要: The amount of chip power that is consumed for cache storage size maintenance is optimized by the close monitoring and control of frequency of missed requests, and the proportion of frequently recurring items to all traffic items. The total number of hit slots is measured per interval of time and is compared to the theoretical value based on random distribution. If the missed rate is high, then the observed effect and value of increasing cache size are deduced by observing how this increase affects the distribution of hits on all cache slots. As the number of frequently hit items in proportion to the total traffic items increases, the benefits of increasing the cache size decreases.

    摘要翻译: 高速缓存存储大小维护所消耗的芯片功率的数量通过密切监视和控制错误请求的频率以及频繁重复的项目与所有流量项目的比例来优化。 每个时间间隔测量命中时隙的总数,并根据随机分布与理论值进行比较。 如果错过率高,则通过观察这种增加如何影响所有高速缓存槽上的命中分布,推导出观察到的增加高速缓存大小的效果和值。 随着与总交通项目成比例的频繁点击项目的数量增加,增加高速缓存大小的好处减少。

    Method and system for processing integrated circuits
    5.
    发明授权
    Method and system for processing integrated circuits 失效
    集成电路处理方法及系统

    公开(公告)号:US06400171B2

    公开(公告)日:2002-06-04

    申请号:US09273895

    申请日:1999-03-22

    IPC分类号: G01R3128

    CPC分类号: G01R31/3004 G01R31/2856

    摘要: A circuit and a method for automatically detecting an operating condition of an integrated circuit chip and for automatically outputting a control signal in response to automatically detecting one of at least two said operating conditions. With the preferred embodiment, FET off currents are reduced during burn-in of a CMOS integrated chip. This is done by a compact, local sensing circuit. The sensing circuit is off during the normal chip operation, and the sensing circuit is only used where needed to provide a local signal to cut down excessive FET off currents. The sensing circuit preferred embodiment is designed with an NFET bandgap device that employs a novel layout approach.

    摘要翻译: 一种用于自动检测集成电路芯片的工作状态并响应于自动检测至少两个所述操作条件之一而自动输出控制信号的电路和方法。 利用优选实施例,在CMOS集成芯片的老化期间,FET截止电流减小。 这是通过紧凑的局部感测电路完成的。 感测电路在正常芯片操作期间关闭,并且感测电路仅在需要时用于提供本地信号以减少过量的FET截止电流。 感测电路优选实施例设计有采用新颖布局方法的NFET带隙器件。