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35 条记录 (耗时 0.016 秒)

    Test mode signal generation circuit
    1.
    发明授权
    Test mode signal generation circuit 有权
    测试模式信号发生电路

    公开(公告)号：US08812920B2

    公开(公告)日：2014-08-19

    申请号：US13604351

    申请日：2012-09-05

    申请人： Yu Ri Lim ,  Min Su Park

    发明人： Yu Ri Lim ,  Min Su Park

    IPC分类号： G11C29/00

    CPC分类号： G06F11/263 ,  G11C29/46

    摘要： A test mode signal generation circuit includes a pre-decoder block configured to output first and second control signals and test address signals in response to first and second address signals, and a signal generation block configured to decode the test address signals in response to the first control signal and generate first and second test mode group signals each including a plurality of test mode signals.

    摘要翻译： 测试模式信号产生电路包括预解码器块，其被配置为响应于第一和第二地址信号而输出第一和第二控制信号和测试地址信号，以及信号产生块，被配置为响应于第一和第二地址信号对测试地址信号进行解码 并产生每个包括多个测试模式信号的第一和第二测试模式组信号。

    Latency control circuit, latency control method thereof, and semiconductor memory device including the same
    4.
    发明授权
    Latency control circuit, latency control method thereof, and semiconductor memory device including the same 有权
    延迟控制电路，其等待时间控制方法和包括该延迟控制电路的半导体存储器件

    公开(公告)号：US08446785B2

    公开(公告)日：2013-05-21

    申请号：US13207979

    申请日：2011-08-11

    申请人： Min-Su Park ,  Jae-II Kim

    发明人： Min-Su Park ,  Jae-II Kim

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1072 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  H03L7/0814

    摘要： A latency control circuit of a semiconductor device includes a phase detection unit configured to generate phase information regarding a phase difference between an external clock and an internal clock, a delay amount deciding unit configured to decide a latency delay amount based on path information of an input signal, a latency value of the input signal, and the phase information, and a latency delay unit configured to generate a latency signal by delaying the input signal according to the latency delay amount and the phase information to produce a delayed input signal and by synchronizing the delayed input signal with the internal clock.

    摘要翻译： 半导体器件的等待时间控制电路包括相位检测单元，被配置为产生关于外部时钟和内部时钟之间的相位差的相位信息;延迟量判定单元，被配置为基于输入的路径信息来决定等待时间延迟量 信号，输入信号的延迟值和相位信息，以及等待时间延迟单元，被配置为通过根据延迟延迟量和相位信息延迟输入信号来产生等待时间信号，以产生延迟的输入信号，并通过同步 具有内部时钟的延迟输入信号。

    Semiconductor device
    6.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08179179B2

    公开(公告)日：2012-05-15

    申请号：US12881541

    申请日：2010-09-14

    申请人： Min-Su Park ,  Hoon Choi

    发明人： Min-Su Park ,  Hoon Choi

    IPC分类号： H03H11/16

    CPC分类号： H03L7/0812 ,  G11C7/222

    摘要： A semiconductor device includes a reset signal generator configured to change the number of activated signals among a plurality of reset signals according to a frequency of an external clock, a plurality of mixing control signal generators configured to generate a plurality of first and second mixing control signals, and a clock mixer configured to generate a mixing clock by mixing a first driving clock and a second driving clock, wherein the first driving clock is generated by driving a positive clock of the external clock according to the plurality of first mixing control signals, and the second driving clock is generated by driving a negative clock of the external clock according to the plurality of second mixing control signals.

    摘要翻译： 半导体器件包括：复位信号发生器，被配置为根据外部时钟的频率改变多个复位信号中的激活信号数;多个混合控制信号发生器，被配置为产生多个第一和第二混合控制信号 以及时钟混频器，被配置为通过混合第一驱动时钟和第二驱动时钟来产生混频时钟，其中通过根据多个第一混频控制信号驱动外部时钟的正时钟来产生第一驱动时钟，以及 通过根据多个第二混合控制信号驱动外部时钟的负时钟来产生第二驱动时钟。

    DELAY LOCKED LOOP CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME
    7.
    发明申请
    DELAY LOCKED LOOP CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME 有权
    延迟锁定环路电路和集成电路，包括它们

    公开(公告)号：US20120007645A1

    公开(公告)日：2012-01-12

    申请号：US12981256

    申请日：2010-12-29

    申请人： Min-Su PARK ,  Hoon Choi

    发明人： Min-Su PARK ,  Hoon Choi

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814

    摘要： A delay locked loop (DLL) circuit includes a timing pulse generating unit configured to generate a plurality of timing pulses, which are sequentially pulsed during delay shifting update periods, in response to a source clock, wherein the number of the generated timing pulses changes according to a frequency of the source clock; a clock delay unit configured to compare a phase of the source clock with a phase of a feedback clock at a time point defined by each of the timing pulses, and delay a phase of an internal clock, corresponding to a rising or falling edge of the source clock, according to the comparison result; and a delay replica modeling unit configured to reflect actual delay conditions of the internal clock path on an output clock of the clock delay unit, and to output the feedback clock.

    摘要翻译： 延迟锁定环（DLL）电路包括定时脉冲发生单元，其被配置为响应于源时钟而在延迟移位更新周期期间产生顺序脉冲的多个定时脉冲，其中所产生的定时脉冲的数量根据 到源时钟的频率; 时钟延迟单元，被配置为将源时钟的相位与由每个定时脉冲定义的时间点的反馈时钟的相位进行比较，并且延迟对应于所述定时脉冲的上升沿或下降沿的内部时钟的相位 源时钟，根据比较结果; 以及延迟复制模型单元，被配置为反映所述时钟延迟单元的输出时钟上的内部时钟路径的实际延迟条件，并输出所述反馈时钟。

    Image forming apparatus and method to operatively control the same
    9.
    发明授权
    Image forming apparatus and method to operatively control the same 有权
    图像形成装置及其操作方法

    公开(公告)号：US07824006B2

    公开(公告)日：2010-11-02

    申请号：US11680808

    申请日：2007-03-01

    申请人： Min-su Park

    发明人： Min-su Park

    IPC分类号： B41J2/165

    CPC分类号： B41J2/16526 ,  B41J2/16535 ,  B41J2/16585

    摘要： An image forming apparatus and method to operatively control the same. The apparatus includes an ink cartridge having a plurality of print heads arranged in a widthwise direction of a print medium, a wiping unit to wipe the print heads while moving in the print medium feeding direction, a positional information providing unit to provide positional information about a position of the wiping unit, and a controller to operatively control the print heads. The controller controls the print heads that, on the basis of the positional information provided and offset information of the ink cartridge, the controller estimates a wiping timing to wipe the nozzles of the print heads with the wiping unit and determines a spitting timing to eject a predetermined amount of ink in the wiped sequence of the nozzles, whereby that the wiping and spitting operations are performed at the estimated wiping timing and the determined spitting timing.

    摘要翻译： 一种可操作地控制该图像形成装置和方法。 该装置包括具有沿打印介质的宽度方向布置的多个打印头的墨盒，在打印介质进给方向移动时擦拭打印头的擦拭单元，提供关于打印介质的位置信息的位置信息提供单元 擦拭单元的位置，以及可操作地控制打印头的控制器。 控制器控制打印头，根据提供的位置信息和墨盒的偏移信息，控制器估计擦拭时间，以便用擦拭单元擦拭打印头的喷嘴，并且确定吐出时间 在喷嘴的擦拭序列中预定量的墨水，从而在估计的擦拭定时和所确定的吐痰时间执行擦拭和吐痰操作。

    System for automatically cleaning and inspecting stud bolt holes, and managing histories of the stud bolt holes
    10.
    发明授权
    System for automatically cleaning and inspecting stud bolt holes, and managing histories of the stud bolt holes 有权
    自动清理和检查双头螺栓孔的系统，以及管柱螺栓孔的历史

    公开(公告)号：US07574770B2

    公开(公告)日：2009-08-18

    申请号：US11551040

    申请日：2006-10-19

    申请人： Sang-Hoon Choi ,  Min-Su Park

    发明人： Sang-Hoon Choi ,  Min-Su Park

    IPC分类号： A47L5/38 ,  A47L5/00

    CPC分类号： B08B9/00 ,  B08B1/04 ,  B08B5/04 ,  F22B37/003 ,  F22B37/005 ,  F22B37/483

    摘要： A system for cleaning and inspecting stud bolt holes, and managing damage histories of the stud bolt holes is disclosed. The system allows an operator to clean stud bolt holes to inspect the stud bolt holes with the naked eye, and manage damage histories of the stud bolt holes. The stud bolt holes fix a nuclear reactor, a nuclear reactor coolant pump head and a pressure vessel main body thereto.

    摘要翻译： 公开了一种用于清洁和检查双头螺栓孔并且管理双头螺栓孔的损坏历史的系统。 该系统允许操作员清洁双头螺栓孔，用肉眼检查双头螺栓孔，并管理双头螺栓孔的损坏历史。 双头螺栓孔将核反应堆，核反应堆冷却剂泵头和压力容器主体固定在其上。