Abstract:
Techniques for using target issue intervals are provided. Request messages may identify the size of a data packet. A target issue interval may be determined based on the request messages. The target issue interval may be used to insert a delay between sending subsequent request messages.
Abstract:
Techniques are provided for performing a delay. A request for a delay may be received. A plurality of delay queues may be provided, with each delay queue spanning a range of delay remaining. The request may be assigned to a delay queue based on the delay remaining. The request may be moved to a different delay queue as the delay remaining decreases.
Abstract:
Techniques described herein provide for sending packets to nodes based on distribution trees with stages. A packet may be received at a node. The stage of the node may be determined. A distribution tree may be selected. Based on the stage and the selected distribution tree, subsequent stage nodes may be determined. The packet may be sent to the subsequent stage nodes.
Abstract:
Techniques for taking corrective action based on probabilities are provided. Request messages may include a size of a data packet and a stated issue interval. A probability of taking corrective action based on the size of the data packet, the stated issue interval, and a target issue interval may be retrieved. Corrective action may be taken with the retrieved probability.
Abstract:
Techniques for delays based on packet sizes are provided. Request messages may identify the size of a data packet. Delays may be initiated based in part on a portion of the size of the data packet. The delays may also be based in part on target issue intervals. Request messages may be sent after the delays.
Abstract:
Techniques described herein provide for sending data packets from source to destination nodes. Indicators, such as counters, may determine the configuration of node interfaces. The data packets may be sent based on a comparison of current and stored indicators.
Abstract:
Techniques described herein provide for sending request messages. The request messages may be sent in order. The request messages may be sent over a designated communications channel.
Abstract:
Embodiments involve an embedded processing element that fetches at least two possible next instructions (control words) in parallel in one cycle, and executes one of them during the following cycle based on the result of a conditional branch test. Embodiments reduce or avoid branch penalties (zero penalty branches).
Abstract:
Compiler-based checkpointing for error recovery. In various embodiments, a compiler is adapted to identify checkpoints in program code. Sets of data objects are associated with the checkpoints, and checkpoint code is generated by the compiler for execution at the checkpoints. The checkpoint code stores state information of the associated data objects for recovery if execution of the program is interrupted.
Abstract:
A computer apparatus incorporating special instructions to force load and store operations to execute in program order. The present invention provides a new and novel store instruction that is suspended until all prior store instructions have been completed by an associated CPU. Also, a new load instruction is provided which blocks any subsequent load instructions from executing until this load instruction has been completed by an associated CPU. These instructions allow for high efficiency computer systems to be implemented which optimize instruction throughput by executing subsequent instructions while waiting for a prior instruction to complete.