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    3-D stacked multiprocessor structure with vertically aligned identical layout operating processors in independent mode or in sharing mode running faster components
    1.
    发明授权
    3-D stacked multiprocessor structure with vertically aligned identical layout operating processors in independent mode or in sharing mode running faster components 有权
    3-D堆叠多处理器结构，具有垂直对齐的相同布局操作处理器，独立模式或共享模式运行更快的组件

    公开(公告)号：US09569402B2

    公开(公告)日：2017-02-14

    申请号：US13452078

    申请日：2012-04-20

    申请人： Alper Buyuktosunoglu ,  Philip G. Emma ,  Allan M. Hartstein ,  Michael B. Healy ,  Krishnan Kunjunny Kailas

    发明人： Alper Buyuktosunoglu ,  Philip G. Emma ,  Allan M. Hartstein ,  Michael B. Healy ,  Krishnan Kunjunny Kailas

    IPC分类号： G06F15/76 ,  G06F15/78 ,  H01L25/065

    CPC分类号： G06F15/7867 ,  H01L25/0657 ,  H01L2924/0002 ,  Y02D10/12 ,  Y02D10/13 ,  H01L2924/00

    摘要： Three-dimensional (3-D) processor structures are provided which are constructed by connecting processors in a stacked configuration. For example, a processor system includes a first processor chip comprising a first processor, and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively configure the first and second processors of the first and second processor chips to operate in one of a plurality of operating modes, wherein the processors can be selectively configured to operate independently, to aggregate resources, to share resources, and/or be combined to form a single processor image.

    摘要翻译： 提供三维（3-D）处理器结构，其通过以堆叠配置连接处理器构成。 例如，处理器系统包括包括第一处理器的第一处理器芯片和包括第二处理器的第二处理器芯片。 第一和第二处理器芯片以堆叠配置连接，第一和第二处理器通过第一和第二处理器芯片之间的垂直连接而连接。 处理器系统还包括模式控制电路，用于选择性地将第一和第二处理器芯片的第一和第二处理器配置为以多种操作模式中的一种操作，其中处理器可以被选择性地配置为独立地操作以聚合资源， 共享资源和/或组合以形成单个处理器映像。

    3-D stacked multiprocessor structures and methods for multimodal operation of same
    2.
    发明授权
    3-D stacked multiprocessor structures and methods for multimodal operation of same 有权
    3-D堆叠多处理器结构和方法用于多模式操作

    公开(公告)号：US09471535B2

    公开(公告)日：2016-10-18

    申请号：US13452113

    申请日：2012-04-20

    申请人： Alper Buyuktosunoglu ,  Philip G. Emma ,  Allan M. Hartstein ,  Michael B. Healy ,  Krishnan Kunjunny Kailas

    发明人： Alper Buyuktosunoglu ,  Philip G. Emma ,  Allan M. Hartstein ,  Michael B. Healy ,  Krishnan Kunjunny Kailas

    IPC分类号： G06F15/00 ,  G06F15/76 ,  G06F15/173 ,  G06F9/38

    CPC分类号： G06F15/17387 ,  G06F9/3802

    摘要： Three-dimensional (3-D) processor devices are provided, which are constructed by connecting processors in a stacked configuration. For instance, a processor system includes a first processor chip comprising a first processor and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively operate the processor system in one of a plurality of operating modes. For example, in a one mode of operation, the first and second processors are configured to implement a run-ahead function, wherein the first processor operates a primary thread of execution and the second processor operates a run-ahead thread of execution.

    摘要翻译： 提供三维（3-D）处理器设备，其通过以堆叠配置连接处理器而构成。 例如，处理器系统包括第一处理器芯片，其包括第一处理器和包括第二处理器的第二处理器芯片。 第一和第二处理器芯片以堆叠配置连接，第一和第二处理器通过第一和第二处理器芯片之间的垂直连接而连接。 处理器系统还包括模式控制电路，用于以多种操作模式之一选择性地操作处理器系统。 例如，在一种操作模式中，第一处理器和第二处理器被配置为实现超前功能，其中第一处理器操作主要执行线程，并且第二处理器操作预先执行的线程。

    3-D stacked multiprocessor structures and methods to enable reliable operation of processors at speeds above specified limits
    4.
    发明授权
    3-D stacked multiprocessor structures and methods to enable reliable operation of processors at speeds above specified limits 有权
    3-D堆叠多处理器结构和方法，以使处理器在高于规定限度的速度下可靠运行

    公开(公告)号：US08826073B2

    公开(公告)日：2014-09-02

    申请号：US13602777

    申请日：2012-09-04

    申请人： Alper Buyuktosunoglu ,  Philip G. Emma ,  Allan M. Hartstein ,  Michael B. Healy ,  Krishnan K. Kailas

    发明人： Alper Buyuktosunoglu ,  Philip G. Emma ,  Allan M. Hartstein ,  Michael B. Healy ,  Krishnan K. Kailas

    IPC分类号： G06F11/00

    CPC分类号： G06F15/7832 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/329 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/24

    摘要： A three-dimensional (3-D) processor system includes a first processor chip and a second processor chip in a stacked configuration. The first processor chip includes a first processor having a first set of state registers. The second processor chip includes a second processor having a second set of state registers that corresponds to the first set of state registers. The first and second processors are connected through vertical connections between the first and second processor chips. A mode control circuit operates the processor system in one of a plurality of operating modes. In one mode of operation, the first processor is active and the second processor is inactive, and the first processor operates at a speed greater than a maximum safe speed of the first processor, and the first processor uses the second set of state registers of the second processor to checkpoint a state of the first processor.

    摘要翻译： 三维（3-D）处理器系统包括堆叠配置的第一处理器芯片和第二处理器芯片。 第一处理器芯片包括具有第一组状态寄存器的第一处理器。 第二处理器芯片包括具有对应于第一组状态寄存器的第二组状态寄存器的第二处理器。 第一和第二处理器通过第一和第二处理器芯片之间的垂直连接连接。 模式控制电路以多种操作模式之一操作处理器系统。 在一种操作模式中，第一处理器是有效的，而第二处理器是不活动的，并且第一处理器以大于第一处理器的最大安全速度的速度操作，并且第一处理器使用第二处理器的第二组状态寄存器 第二处理器来检查第一处理器的状态。

    3-D stacked multiprocessor structure with vertically aligned identical layout operating processors in independent mode or in sharing mode running faster components
    7.
    发明授权
    3-D stacked multiprocessor structure with vertically aligned identical layout operating processors in independent mode or in sharing mode running faster components 有权
    3-D堆叠多处理器结构，具有垂直对齐的相同布局操作处理器，独立模式或共享模式运行更快的组件

    公开(公告)号：US09298672B2

    公开(公告)日：2016-03-29

    申请号：US13602807

    申请日：2012-09-04

    申请人： Alper Buyuktosunoglu ,  Philip G. Emma ,  Allan M. Hartstein ,  Michael B. Healy ,  Krishnan Kunjunny Kailas

    发明人： Alper Buyuktosunoglu ,  Philip G. Emma ,  Allan M. Hartstein ,  Michael B. Healy ,  Krishnan Kunjunny Kailas

    IPC分类号： G06F15/16 ,  H01L25/065 ,  G06F15/78

    CPC分类号： G06F15/7867 ,  H01L25/0657 ,  H01L2924/0002 ,  Y02D10/12 ,  Y02D10/13 ,  H01L2924/00

    摘要： Three-dimensional (3-D) processor structures are provided which are constructed by connecting processors in a stacked configuration. For example, a processor system includes a first processor chip comprising a first processor, and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively configure the first and second processors of the first and second processor chips to operate in one of a plurality of operating modes, wherein the processors can be selectively configured to operate independently, to aggregate resources, to share resources, and/or be combined to form a single processor image.

    摘要翻译： 提供三维（3-D）处理器结构，其通过以堆叠配置连接处理器构成。 例如，处理器系统包括包括第一处理器的第一处理器芯片和包括第二处理器的第二处理器芯片。 第一和第二处理器芯片以堆叠配置连接，第一和第二处理器通过第一和第二处理器芯片之间的垂直连接而连接。 处理器系统还包括模式控制电路，用于选择性地将第一和第二处理器芯片的第一和第二处理器配置为以多种操作模式中的一种操作，其中处理器可以被选择性地配置为独立地操作以聚合资源， 共享资源和/或组合以形成单个处理器映像。

    3-D STACKED MULTIPROCESSOR STRUCTURES AND METHODS FOR MULTIMODAL OPERATION OF SAME
    9.
    发明申请
    3-D STACKED MULTIPROCESSOR STRUCTURES AND METHODS FOR MULTIMODAL OPERATION OF SAME 有权
    3-D堆叠多处理器结构及其多种操作方法

    公开(公告)号：US20130283010A1

    公开(公告)日：2013-10-24

    申请号：US13601289

    申请日：2012-08-31

    申请人： Alper Buyuktosunoglu ,  Philip G. Emma ,  Allan M. Hartstein ,  Michael B. Healy ,  Krishnan Kunjunny Kailas

    发明人： Alper Buyuktosunoglu ,  Philip G. Emma ,  Allan M. Hartstein ,  Michael B. Healy ,  Krishnan Kunjunny Kailas

    IPC分类号： G06F15/76

    CPC分类号： G06F15/17387 ,  G06F9/3802

    摘要： Three-dimensional (3-D) processor devices are provided, which are constructed by connecting processors in a stacked configuration. For instance, a processor system includes a first processor chip comprising a first processor and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively operate the processor system in one of a plurality of operating modes. For example, in a one mode of operation, the first and second processors are configured to implement a run-ahead function, wherein the first processor operates a primary thread of execution and the second processor operates a run-ahead thread of execution.

    摘要翻译： 提供三维（3-D）处理器设备，其通过以堆叠配置连接处理器而构成。 例如，处理器系统包括第一处理器芯片，其包括第一处理器和包括第二处理器的第二处理器芯片。 第一和第二处理器芯片以堆叠配置连接，第一和第二处理器通过第一和第二处理器芯片之间的垂直连接而连接。 处理器系统还包括模式控制电路，用于以多种操作模式之一选择性地操作处理器系统。 例如，在一种操作模式中，第一处理器和第二处理器被配置为实现超前功能，其中第一处理器操作主要执行线程，并且第二处理器操作预先执行的线程。