公开(公告)号：US08829990B2

公开(公告)日：2014-09-09

申请号：US13595141

申请日：2012-08-27

申请人： Douglas E. Heineman ,  Mark A. Alexander

发明人： Douglas E. Heineman ,  Mark A. Alexander

IPC分类号： H03F3/38 ,  H03F3/217 ,  H03F3/189 ,  H03F1/26 ,  H03K5/003

CPC分类号： H03G3/3026 ,  H03F1/26 ,  H03F3/185 ,  H03F3/189 ,  H03F3/2173 ,  H03F3/45 ,  H03F3/45179 ,  H03F2200/03 ,  H03G1/04 ,  H03K5/003

摘要： An amplifier may include two or more pulse-width modulators controlling respective sets of switches to produce an amplified version of a source signal. A positive DC-offset based on the source signal may be applied to the pulse-width modulator controlling one respective set of switches, and an equal value negative DC-offset may be applied to the pulse-width modulator controlling the other respective set of switches, to provide an effective offset between the respective points in time of the rising/falling edges of the different pulse-width modulated control signals. The addition of alternating positive and negative DC-offset values doesn't affect the output load, and doesn't degrade the signal. The DC-offsets may be added at a frequency selected to be beyond the signal baseband, and the value of the small input signal level may be determined using an RMS level comparator or similar measurement technique.

摘要翻译： 放大器可以包括两个或更多个脉冲宽度调制器，其控制各组开关以产生源信号的放大版本。 可以将基于源极信号的正DC偏移施加到控制一组相应开关的脉冲宽度调制器，并且可以将相等值的负DC偏移施加到控制另一组开关的脉宽调制器 以提供不同脉冲宽度调制控制信号的上升/下降沿的各个时间点之间的有效偏移。 交替的正和负DC偏移值的添加不会影响输出负载，也不会降低信号。 可以以选择为超出信号基带的频率添加DC偏移，并且可以使用RMS电平比较器或类似的测量技术来确定小输入信号电平的值。

公开(公告)号：US20130088296A1

公开(公告)日：2013-04-11

申请号：US13595276

申请日：2012-08-27

申请人： Douglas E. Heineman ,  Mark A. Alexander

发明人： Douglas E. Heineman ,  Mark A. Alexander

IPC分类号： H03F1/32 ,  H03F3/217

CPC分类号： H03G3/3026 ,  H03F1/26 ,  H03F3/185 ,  H03F3/189 ,  H03F3/2173 ,  H03F3/45 ,  H03F3/45179 ,  H03F2200/03 ,  H03G1/04 ,  H03K5/003

摘要： An amplifier may include two or more pulse-width modulators (PWMs) controlling respective sets of switches to produce an amplified version of a source signal. The clocking for the amplifier may be controlled to delay signal processing within the PWMs relative to one another in time, thereby providing an effective time offset between the respective edge transitions of the controlling signals provided to the respective sets of switches. The PWMs may count down to zero from the next PWM duty-cycle value when a new data sample is detected, beginning a new count for each new sample, with the PWM outputting a pulse when the counter value is nonzero. A “data-sample-ready” signal may be decoded from a master counter, which may be clocked based on the high speed PWM clock, and the decode value may be adjusted to determine when the PWM should initialize to the next data sample.

摘要翻译： 放大器可以包括两个或更多个脉冲宽度调制器（PWM），其控制各组开关以产生源信号的放大版本。 可以控制放大器的时钟以在时间上相对于彼此延迟PWM内的信号处理，从而在提供给各组开关的控制信号的各个边沿跃迁之间提供有效的时间偏移。 当检测到新的数据采样时，PWM可以从下一个PWM占空比值倒数为零，开始每个新采样的新计数，当计数器值为非零时，PWM输出脉冲。 数据采样就绪信号可以从主计数器解码，主计数器可以基于高速PWM时钟进行计时，并且可以调整解码值以确定PWM应该何时初始化到下一个数据采样。

公开(公告)号：US08412497B1

公开(公告)日：2013-04-02

申请号：US12876967

申请日：2010-09-07

申请人： Mark A. Alexander

发明人： Mark A. Alexander

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F2217/82

摘要： Predicting simultaneous switching output noise of an IC device is described. User input is obtained. The user input includes: an identification of an input/output bank of an integrated circuit die; an identification of a device package substrate to which the integrated circuit die is to be attached; and an identification of input/output interface to be used by the input/output bank. A noise factor and an impedance are selected responsive to the user input. The noise factor is multiplied with the impedance to provide a result. The result, which is output, is a prediction of the simultaneous switching output noise of the integrated circuit device.

摘要翻译： 描述了IC设备的同时切换输出噪声的预测。 获取用户输入。 用户输入包括：集成电路管芯的输入/输出组的标识; 集成电路芯片要附着到的器件封装基板的识别; 以及由输入/输出组使用的输入/输出接口的识别。 响应于用户输入选择噪声因子和阻抗。 噪声因子与阻抗相乘以提供结果。 输出的结果是对集成电路器件的同时开关输出噪声的预测。

公开(公告)号：US07949979B1

公开(公告)日：2011-05-24

申请号：US12190729

申请日：2008-08-13

申请人： Mark A. Alexander

发明人： Mark A. Alexander

IPC分类号： G06F17/50

CPC分类号： G06F17/50 ,  G06F17/5036 ,  G06F17/5054 ,  G06F2217/40 ,  G06F2217/82

摘要： Induced crosstalk is predicted for the input/output pins of a programmable logic device. Signal edge rates for the input/output pin are determined from selected interface protocols for the input/output pins. For each pair of the input/output pins, a first coupling coefficient specifies a coupling between the pair of input/output pins within a package for mounting the programmable logic device to a printed circuit board. A depth is input for each via coupled to an input/output pin by the printed circuit board. From the via depths, a second coupling coefficient is determined for each pair of the input/output pins that satisfy a separation criterion. For each of the input/output pins, a predicted value of an induced crosstalk is determined from the first and second coupling coefficients for each pair that includes the input/output pin and another input/output pin, and from the signal edge rate of this other input/output pin.

摘要翻译： 针对可编程逻辑器件的输入/输出引脚预测引起的串扰。 输入/输出引脚的信号边沿率由输入/输出引脚的选定接口协议决定。 对于每对输入/输出引脚，第一耦合系数指定用于将可编程逻辑器件安装到印刷电路板的封装内的一对输入/输出引脚之间的耦合。 对于通过印刷电路板耦合到输入/输出引脚的每个通孔输入深度。 从通孔深度，确定满足分离标准的每对输入/输出引脚的第二耦合系数。 对于每个输入/输出引脚，从包括输入/​​输出引脚和另一个输入/输出引脚的每对的第一和第二耦合系数确定感应串扰的预测值，并根据该输入/输出引脚的信号边沿速率 其他输入/输出引脚。

公开(公告)号：US07915864B2

公开(公告)日：2011-03-29

申请号：US12815609

申请日：2010-06-15

申请人： Mark A. Alexander

发明人： Mark A. Alexander

IPC分类号： H02J7/04 ,  G05F1/00

CPC分类号： H02M3/156 ,  H02M1/38 ,  H02M2001/008

摘要： Transient processing mechanisms for power converters. Error generation circuitry in a power converter may generate an error signal based on the difference between a power converter output voltage and a reference voltage. Transient detection circuitry may detect whether the error signal exceeds at least a first threshold. If the first threshold is exceeded, timing control logic may generate a low band correction pulse to adjust the power converter output voltage, and thereby adjust the error signal to a level within the first threshold. If the error signal exceeds a second threshold, the timing control logic may generate a high band correction pulse to adjust the power converter output voltage, and thereby adjust the error signal to a level within the second threshold. The timing control logic may initiate a low band blanking period following the low band correction pulse and high band blanking period following the high band correction pulse.

摘要翻译： 电源转换器的瞬态处理机制。 功率转换器中的误差产生电路可以基于功率转换器输出电压和参考电压之间的差异产生误差信号。 瞬态检测电路可以检测误差信号是否超过至少第一阈值。 如果超过第一阈值，则定时控制逻辑可以产生低频带校正脉冲以调整功率转换器输出电压，从而将误差信号调整到第一阈值内的电平。 如果误差信号超过第二阈值，则定时控制逻辑可以产生高频带校正脉冲以调整功率转换器输出电压，从而将误差信号调整到第二阈值内的电平。 定时控制逻辑可以在高频带校正脉冲和高频带校正脉冲之后的低频带校正脉冲和高频带消隐周期之后发起低频消隐周期。

公开(公告)号：US20090237056A1

公开(公告)日：2009-09-24

申请号：US12477706

申请日：2009-06-03

申请人： Mark A. Alexander

发明人： Mark A. Alexander

IPC分类号： G05F1/10

CPC分类号： H02M3/156 ,  H02M1/38 ,  H02M2001/008

摘要： Transient processing mechanisms for power converters. Error generation circuitry in a power converter may generate an error signal based on the difference between a power converter output voltage and a reference voltage. Transient detection circuitry may detect whether the error signal exceeds at least a first threshold. If the first threshold is exceeded, timing control logic may generate a low band correction pulse to adjust the power converter output voltage, and thereby adjust the error signal to a level within the first threshold. If the error signal exceeds a second threshold, the timing control logic may generate a high band correction pulse to adjust the power converter output voltage, and thereby adjust the error signal to a level within the second threshold. The timing control logic may initiate a low band blanking period following the low band correction pulse and high band blanking period following the high band correction pulse.

摘要翻译： 电源转换器的瞬态处理机制。 功率转换器中的误差产生电路可以基于功率转换器输出电压和参考电压之间的差异产生误差信号。 瞬态检测电路可以检测误差信号是否超过至少第一阈值。 如果超过第一阈值，则定时控制逻辑可以产生低频带校正脉冲以调整功率转换器输出电压，从而将误差信号调整到第一阈值内的电平。 如果误差信号超过第二阈值，则定时控制逻辑可以产生高频带校正脉冲以调整功率转换器输出电压，从而将误差信号调整到第二阈值内的电平。 定时控制逻辑可以在高频带校正脉冲和高频带校正脉冲之后的低频带校正脉冲和高频带消隐周期之后发起低频消隐周期。

公开(公告)号：US20150063593A1

公开(公告)日：2015-03-05

申请号：US14490459

申请日：2014-09-18

申请人： Douglas E. Heineman ,  Mark A. Alexander

发明人： Douglas E. Heineman ,  Mark A. Alexander

IPC分类号： H03G3/30 ,  H03G1/04

CPC分类号： H03G3/3026 ,  H03F1/26 ,  H03F3/185 ,  H03F3/189 ,  H03F3/2173 ,  H03F3/45 ,  H03F3/45179 ,  H03F2200/03 ,  H03G1/04 ,  H03K5/003

摘要： An amplifier may include two or more pulse-width modulators (PWMs) controlling respective sets of switches to produce an amplified version of a source signal. The clocking for the amplifier may be controlled to delay signal processing within the PWMs relative to one another in time, thereby providing an effective time offset between the absolute moment in time of the edge transition of the controlling signals to the respective sets of switches. The PWMs may include a decrementor that counts down to zero from the next PWM duty-cycle value when a new data sample is detected, beginning a new count when the next sample is present. The PWM output may correspond to the counter value, outputting a pulse when the counter value is nonzero. A “data-sample-ready” signal may be decoded from a master counter, which may be clocked based on the high speed PWM clock, and the delay mechanism may be based on adjusting the decode value to determine when the PWM should initialize to the next data sample.

摘要翻译： 放大器可以包括两个或更多个脉冲宽度调制器（PWM），其控制各组开关以产生源信号的放大版本。 可以控制放大器的时钟，以在时间上相对于彼此延迟PWM内的信号处理，从而在控制信号的边沿转换到相应的开关组之间的绝对时刻之间提供有效的时间偏移。 当检测到新的数据样本时，PWM可以包括从下一个PWM占空比值向下递减到零的递减器，当存在下一个采样时，开始新的计数。 PWM输出可对应于计数器值，当计数器值不为零时输出脉冲。 可以从主计数器解码“数据采样就绪”信号，该主计数器可以基于高速PWM时钟来计时，并且延迟机制可以基于调整解码值来确定PWM何时应该初始化为 下一个数据样本。

公开(公告)号：US07755381B1

公开(公告)日：2010-07-13

申请号：US12359902

申请日：2009-01-26

申请人： Peter H. Alfke ,  Mark A. Alexander

发明人： Peter H. Alfke ,  Mark A. Alexander

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03K19/00361

摘要： An IC uses a tunable interconnect driver between a data source and a data destination to selectively slow down (“de-tune”) data signals. Data sent along relatively short paths are de-tuned to reduce power supply noise during synchronous switching events. In some embodiments, the tunable interconnect driver delays data transmission relative to an un-delayed signal path, in other embodiments, the slew rate of the tunable interconnect driver is selectively reduced.

摘要翻译： IC使用数据源和数据目的地之间的可调谐互连驱动器来选择性地减慢（“调整”）数据信号。 沿相对较短路径发送的数据被去调整，以减少同步切换事件期间的电源噪声。 在一些实施例中，可调谐互连驱动器相对于未延迟的信号路径延迟数据传输，在其他实施例中，可选择性地减少可调谐互连驱动器的转换速率。

公开(公告)号：US07511299B1

公开(公告)日：2009-03-31

申请号：US11906669

申请日：2007-10-02

申请人： Mark A. Alexander ,  Paul Ying-Fung Wu

发明人： Mark A. Alexander ,  Paul Ying-Fung Wu

IPC分类号： H01L23/58

CPC分类号： H01L23/66 ,  H01L22/32 ,  H01L2223/6627 ,  H01L2224/16 ,  H01L2924/15311 ,  H01L2924/1903 ,  H01L2924/19105 ,  H01L2924/3011

摘要： A packaged integrated circuit (“IC”) includes a substrate, an IC die, and a molded plastic lid. A test point standoff is electrically connected to the IC die and extends away from the surface of the package substrate through the molded plastic lid toward the top surface of the molded plastic lid. The top of the test point standoff is below the top surface of the molded plastic lid.

摘要翻译： 封装集成电路（“IC”）包括基板，IC管芯和模制塑料盖。 测试点间隔电连接到IC管芯，并通过模塑塑料盖朝模塑塑料盖的顶表面远离封装衬底的表面延伸。 测试点支架的顶部位于模制塑料盖的顶部表面之下。

公开(公告)号：US07138815B1

公开(公告)日：2006-11-21

申请号：US10746587

申请日：2003-12-24

申请人： Mark A. Alexander ,  Sean A. Koontz

发明人： Mark A. Alexander ,  Sean A. Koontz

IPC分类号： G01R31/02

CPC分类号： G01R31/2856 ,  G01R31/2853 ,  G01R31/3004 ,  G01R31/31721

摘要： A packaged semiconductor device uses built-in self test to characterize voltage between points within the semiconductor die during a current discontinuity generated in the semiconductor die. The semiconductor die is operated to generate a current discontinuity, or several sequential current discontinuities, and the voltage is measured with an on-chip ADC. Measuring the voltage within the semiconductor die, rather than measuring at external test points, provides a more accurate prediction of device operation. Multiple test points are measured using a multiplexer, multiple ADCs, or by reconfiguring an FPGA. Impedance versus frequency information of the greater power distribution system connected to the semiconductor die is obtained by transforming the voltage and current through the semiconductor die measured during a current discontinuity.

摘要翻译： 封装的半导体器件在半导体管芯内产生的电流不连续性中使用内置的自我测试来表征半导体管芯内的点之间的电压。 操作半导体管芯以产生电流不连续性或几个连续的电流不连续性，并且使用片上ADC测量电压。 测量半导体管芯内的电压，而不是在外部测试点进行测量，可以更准确地预测器件的工作。 使用多路复用器，多个ADC或通过重新配置FPGA来测量多个测试点。 通过转换在电流不连续期间测量的通过半导体管芯的电压和电流来获得连接到半导体管芯的较大配电系统的阻抗与频率信息。