公开(公告)号：US20200310798A1

公开(公告)日：2020-10-01

申请号：US16367409

申请日：2019-03-28

Applicant: Manjunath Shevgoor ,  Mark Joseph Dechene ,  Vineeth Mekkat ,  Jason Michael Agron ,  Zhongying Zhang

Inventor： Manjunath Shevgoor ,  Mark Joseph Dechene ,  Vineeth Mekkat ,  Jason Michael Agron ,  Zhongying Zhang

IPC: G06F9/30 ,  G06F9/38

Abstract: An integrated circuit with support for memory atomicity comprises a processor core. The processor core comprises a data cache unit (DCU), a store buffer (SB), a retirement unit, and memory atomicity facilities. The memory atomicity facilities are configured, when engaged, to (a) add an SB entry to the SB, in response to the processor core executing a store instruction that is part of an atomic region of code; (b) cause the SB entry to become senior, in response to the retirement unit retiring the store instruction; and (c) cause the SB entry to become walk enabled, in response to the retirement unit committing a transaction associated with the atomic region. Other embodiments are described and claimed.

公开(公告)号：US20190303150A1

公开(公告)日：2019-10-03

申请号：US15941976

申请日：2018-03-30

Applicant: Mark Dechene ,  Manjunath Shevgoor ,  Faruk Guvenilir ,  Zhongying Zhang ,  Jonathan Perry

Inventor： Mark Dechene ,  Manjunath Shevgoor ,  Faruk Guvenilir ,  Zhongying Zhang ,  Jonathan Perry

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/1027

Abstract: An apparatus and method for early page address prediction. For example, one embodiment of a processor comprises: an instruction fetch circuit to fetch a load instruction; a decoder to decode the load instruction; execution circuitry to execute the load instruction to perform a load operation, the execution circuitry including an address generation unit (AGU) to generate an effective address to be used for the load operation; and early page prediction (EPP) circuitry to use one or more attributes associated with the load instruction to predict a physical page address for the load instruction simultaneously with the AGU generating the effective address and/or prior to generation of the effective address.