公开(公告)号：US08019948B2

公开(公告)日：2011-09-13

申请号：US12909069

申请日：2010-10-21

申请人： Chi-Sung Oh ,  Yong-Jun Kim ,  Kyung-Woo Nam ,  Jin-Kuk Kim ,  Soo-Young Kim

发明人： Chi-Sung Oh ,  Yong-Jun Kim ,  Kyung-Woo Nam ,  Jin-Kuk Kim ,  Soo-Young Kim

IPC分类号： G06F12/00 ,  G11C5/06

CPC分类号： G11C5/02 ,  G11C8/12

摘要： A multipath accessible semiconductor memory device having a mailbox area and a mailbox access control method thereof are provided. The semiconductor memory device includes N number of ports, at least one shared memory area allocated in a memory cell array, and N number of mailbox areas for message communication. The at least one shared memory area is operationally connected to the N number of ports, and is accessible through a plurality of data input/output lines to form a data access path between the at least one shared memory area and one port, having an access right to the at least one memory area, among the N number of ports. The N number of mailbox areas are provided in one-to-one correspondence with the N number of ports and are accessible through the plurality of data input/output lines when an address of a predetermined area of the at least one shared memory area is applied to the semiconductor memory device. An efficient layout of mailboxes and an efficient message access path can be obtained.

摘要翻译： 提供具有邮箱区域和邮箱访问控制方法的多路径可访问半导体存储装置。 半导体存储器件包括N个端口，分配在存储单元阵列中的至少一个共享存储区域和N个用于消息通信的邮箱区域。 所述至少一个共享存储区域可操作地连接到所述N个端口，并且可通过多个数据输入/输出线路访问，以在所述至少一个共享存储区域和一个端口之间形成数据访问路径， 在N个端口中的至少一个存储区域的权限。 N个邮箱区域与N个端口一一对应地提供，并且当应用至少一个共享存储区域的预定区域的地址时可以通过多个数据输入/输出线路访问邮箱区域 到半导体存储器件。 可以获得邮箱的有效布局和高效的邮件访问路径。

公开(公告)号：US07840762B2

公开(公告)日：2010-11-23

申请号：US11843877

申请日：2007-08-23

申请人： Chi-Sung Oh ,  Yong-Jun Kim ,  Kyung-Woo Nam ,  Jin-Kuk Kim ,  Soo-Young Kim

发明人： Chi-Sung Oh ,  Yong-Jun Kim ,  Kyung-Woo Nam ,  Jin-Kuk Kim ,  Soo-Young Kim

IPC分类号： G06F12/00

CPC分类号： G11C5/02 ,  G11C8/12

摘要： A multipath accessible semiconductor memory device having a mailbox area and a mailbox access control method thereof are provided. The semiconductor memory device includes N number of ports, at least one shared memory area allocated in a memory cell array, and N number of mailbox areas for message communication. The at least one shared memory area is operationally connected to the N number of ports, and is accessible through a plurality of data input/output lines to form a data access path between the at least one shared memory area and one port, having an access right to the at least one memory area, among the N number of ports. The N number of mailbox areas are provided in one-to-one correspondence with the N number of ports and are accessible through the plurality of data input/output lines when an address of a predetermined area of the at least one shared memory area is applied to the semiconductor memory device. An efficient layout of mailboxes and an efficient message access path can be obtained.

摘要翻译： 提供具有邮箱区域和邮箱访问控制方法的多路径可访问半导体存储装置。 半导体存储器件包括N个端口，分配在存储单元阵列中的至少一个共享存储区域和N个用于消息通信的邮箱区域。 所述至少一个共享存储区域可操作地连接到所述N个端口，并且可通过多个数据输入/输出线路访问，以在所述至少一个共享存储区域和一个端口之间形成数据访问路径， 在N个端口中的至少一个存储区域的权限。 N个邮箱区域与N个端口一一对应地提供，并且当应用至少一个共享存储区域的预定区域的地址时可以通过多个数据输入/输出线路访问邮箱区域 到半导体存储器件。 可以获得邮箱的有效布局和高效的邮件访问路径。

公开(公告)号：US07555625B2

公开(公告)日：2009-06-30

申请号：US11260008

申请日：2005-10-27

申请人： Kyung-Woo Nam

发明人： Kyung-Woo Nam

IPC分类号： G06F13/00 ,  G06F13/28 ,  G11C8/10

CPC分类号： G06F13/4234

摘要： A multi-memory chip and data transfer method are capable of directly transferring data between internal memory devices. The multi-memory chip of the present invention includes a first memory device, a second memory device, and a data transmission bus that is shared by the memory devices. Furthermore, the second memory device includes a mode register set for setting an internal transfer mode. In accordance with the data transfer method according to the present invention, the transfer of data between the memory devices included in the multi-memory chip is performed through the data transmission bus shared by the memory devices. Accordingly, the multi-memory chip and the data transfer method can considerably improve data transfer rates between devices, as compared to conventional approaches in which data is transferred to the DMA controller of an external system.

摘要翻译： 多存储器芯片和数据传输方法能够在内部存储器件之间直接传送数据。 本发明的多存储器芯片包括由存储器件共享的第一存储器件，第二存储器件和数据传输总线。 此外，第二存储器件包括用于设置内部传送模式的模式寄存器组。 根据本发明的数据传输方法，通过由存储器件共享的数据传输总线来执行包括在多存储器芯片中的存储器件之间的数据传输。 因此，与将数据传送到外部系统的DMA控制器的传统方式相比，多存储器芯片和数据传输方法可以显着地提高设备之间的数据传输速率。

公开(公告)号：US20090106503A1

公开(公告)日：2009-04-23

申请号：US11977047

申请日：2007-10-23

申请人： Dong-Hyuk Lee ,  Kyung-Woo Nam ,  Yong-Jun Kim ,  Jong-Wook Park ,  Chi-Sung Oh

发明人： Dong-Hyuk Lee ,  Kyung-Woo Nam ,  Yong-Jun Kim ,  Jong-Wook Park ,  Chi-Sung Oh

IPC分类号： G06F12/14

CPC分类号： G11C11/406 ,  G11C7/1075 ,  G11C11/40603 ,  G11C11/40618

摘要： A multi-port memory device includes a refresh register and a refresh controller for preventing refresh starvation in a shared memory unit of the memory device. The memory device further includes a plurality of ports sharing access to the shared memory unit. The refresh register stores information regarding at least one refresh command. The refresh controller determines whether to activate an internal refresh operation at a transition in port authority according to such information stored in the refresh register.

摘要翻译： 多端口存储器件包括刷新寄存器和刷新控制器，用于防止存储器件的共享存储器单元中的刷新不足。 存储装置还包括共享对共享存储器单元的访问的多个端口。 刷新寄存器存储关于至少一个刷新命令的信息。 刷新控制器根据存储在刷新寄存器中的信息来确定是否在端口权限转换时激活内部刷新操作。

公开(公告)号：US20080170460A1

公开(公告)日：2008-07-17

申请号：US11843877

申请日：2007-08-23

申请人： Chi-Sung OH ,  Yong-Jun Kim ,  Kyung-Woo Nam ,  Jin-Kuk Kim

发明人： Chi-Sung OH ,  Yong-Jun Kim ,  Kyung-Woo Nam ,  Jin-Kuk Kim

IPC分类号： G11C8/16 ,  G06F12/00

CPC分类号： G11C5/02 ,  G11C8/12

摘要： A multipath accessible semiconductor memory device having a mailbox area and a mailbox access control method thereof are provided. The semiconductor memory device includes N number of ports, at least one shared memory area allocated in a memory cell array, and N number of mailbox areas for message communication. The at least one shared memory area is operationally connected to the N number of ports, and is accessible through a plurality of data input/output lines to form a data access path between the at least one shared memory area and one port, having an access right to the at least one memory area, among the N number of ports. The N number of mailbox areas are provided in one-to-one correspondence with the N number of ports and are accessible through the plurality of data input/output lines when an address of a predetermined area of the at least one shared memory area is applied to the semiconductor memory device. An efficient layout of mailboxes and an efficient message access path can be obtained.

摘要翻译： 提供具有邮箱区域和邮箱访问控制方法的多路径可访问半导体存储装置。 半导体存储器件包括N个端口，分配在存储单元阵列中的至少一个共享存储区域和N个用于消息通信的邮箱区域。 所述至少一个共享存储区域可操作地连接到所述N个端口，并且可通过多个数据输入/输出线路访问，以在所述至少一个共享存储区域和一个端口之间形成数据访问路径， 在N个端口中的至少一个存储区域的权限。 N个邮箱区域与N个端口一一对应地提供，并且当应用至少一个共享存储区域的预定区域的地址时可以通过多个数据输入/输出线路访问邮箱区域 到半导体存储器件。 可以获得邮箱的有效布局和高效的邮件访问路径。

公开(公告)号：US07440352B2

公开(公告)日：2008-10-21

申请号：US11339734

申请日：2006-01-26

申请人： Kyung-woo Nam

发明人： Kyung-woo Nam

IPC分类号： G11C7/00

CPC分类号： G11C8/08 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40622

摘要： A semiconductor memory device comprises a plurality of memory cells connected to a plurality of word lines grouped in word line sets. Each of the word line sets is connected to a word line enable signal generation unit which stores information indicating whether data has been written to any of the memory cells connected to the word line set. The word line enable signal generation unit controls refresh operations for memory cells connected to the word line set so that only word lines connected to memory cells that have been programmed are refreshed.

摘要翻译： 半导体存储器件包括连接到分组在字线组中的多个字线的多个存储器单元。 每个字线组连接到字线使能信号生成单元，该单元存储指示数据是否被写入连接到字线组的任何存储单元的信息。 字线使能信号发生单元控制连接到字线组的存储单元的刷新操作，使得只有连接到已被编程的存储器单元的字线被刷新。

公开(公告)号：US06928016B2

公开(公告)日：2005-08-09

申请号：US10359531

申请日：2003-02-05

申请人： Kyung-Woo Nam ,  Song-Won Kim

发明人： Kyung-Woo Nam ,  Song-Won Kim

IPC分类号： G11C11/401 ,  G11C11/406 ,  G11C7/00

CPC分类号： G11C11/40603 ,  G11C11/406 ,  G11C11/40615 ,  G11C2211/4061

摘要： In the refresh type semiconductor memory device having a plurality of refresh type memory cells, for internally performing a refresh operation without an external command together with an input and output operation of data; the refresh type semiconductor memory device includes a refresh circuit having a compulsive refresh request signal generator that disables a refresh request cut-off signal, in response to a signal responding to an active transition of a write enable signal, and a dummy refresh signal generated in a read operation, so as to prevent a refresh fail causable in a consecutive write operation, whereby improving a write cycle time and minimizing a refresh fail at a high speed operation.

摘要翻译： 在具有多个刷新型存储单元的刷新型半导体存储器件中，用于内部执行没有外部指令的刷新操作以及数据的输入和输出操作; 刷新型半导体存储器件包括具有强制刷新请求信号发生器的刷新电路，该强制刷新请求信号发生器响应于响应于写使能信号的有源转换的信号和在其中产生的虚拟刷新信号而禁用刷新请求截止信号 读取操作，以防止在连续写入操作中导致刷新失败，由此在高速操作时提高写入周期时间并使刷新最小化失败。

公开(公告)号：US06633995B1

公开(公告)日：2003-10-14

申请号：US09522310

申请日：2000-03-09

申请人： Kyung Woo Nam

发明人： Kyung Woo Nam

IPC分类号： G06F104

CPC分类号： G11C7/222 ,  G06F9/3869 ,  G11C7/1039

摘要： A high-speed pipeline device includes n data path circuits connected in cascade between an input terminal and an output terminal. N data passing circuits have transmission times {T1, . . . , Tn} each less than a period P of a reference clock signal, at least one of the transmission times differing from another. N pipe registers connect to the input terminals of the data path circuits to latch data passed from a previous stage or the input terminal. A control signal generating circuit produces n pipeline control signals in response to the reference clock signal. N−1 of the pipeline control signals are generated in cascade from preceding pipeline control signals, and an (n)th pipeline control signal is generated directly from the reference clock signal. The control signal generating circuit provides the n pipeline control signals to the n pipe register, so that the total transmission time from the input terminals to the output terminals is minimal. Accordingly, the device can output the valid data within the shortest time by generating pipeline control signals of each stage with a minimum margin for possible changes of a temperature and power supply voltage.

摘要翻译： 高速流水线装置包括在输入端子和输出端子之间级联连接的n条数据路径电路。 N个数据传送电路具有传输时间{T 1 ，。 。 。 ，Tn}，每个小于参考时钟信号的周期P，至少一个传输时间与另一个不同。 N个管路寄存器连接到数据路径电路的输入端，以锁存从前一级或输入端传来的数据。 控制信号发生电路响应于参考时钟信号产生n个流水线控制信号。 从先前的流水线控制信号级联产生流水线控制信号的N-1，并且从参考时钟信号直接生成第（n）个流水线控制信号。 控制信号发生电路向n管寄存器提供n个流水线控制信号，使得从输入端到输出端的总传输时间最小。 因此，设备可以在最短时间内通过产生每个级的流水线控制信号来输出有效数据，并具有可能的温度和电源电压变化的最小余量。

公开(公告)号：US06542425B2

公开(公告)日：2003-04-01

申请号：US09558321

申请日：2000-04-26

申请人： Kyung-woo Nam

发明人： Kyung-woo Nam

IPC分类号： G11C700

CPC分类号： G11C11/406

摘要： A refresh control circuit is provided for controlling refresh cycles according to values stored in a register. A related refreshing method is also provided. The refresh control circuit controls the refresh cycles so as to refresh data stored in memory cells. The refresh control circuit includes a refresh counter for generating a plurality of frequency division signals by dividing a clock signal in response to a refresh signal for directing a refresh operation. The refresh control circuit also includes a refresh activation signal generator for generating a refresh activation signal corresponding to the refresh cycle according to values stored in a register.

公开(公告)号：US08122199B2

公开(公告)日：2012-02-21

申请号：US12392432

申请日：2009-02-25

申请人： Jin-Hyoung Kwon ,  Kyung-Woo Nam ,  Han-Gu Sohn ,  Ho-Cheol Lee ,  Kwang-Myeong Jang

发明人： Jin-Hyoung Kwon ,  Kyung-Woo Nam ,  Han-Gu Sohn ,  Ho-Cheol Lee ,  Kwang-Myeong Jang

IPC分类号： G06F12/00

CPC分类号： G11C11/413 ,  G11C7/1075

摘要： A multiport semiconductor memory device includes; first and second port units respectively coupled to first and second processors, first and second dedicated memory area accessed by first and second processors, respectively and implemented using DRAM cells, a shared memory area commonly accessed by the first and second processors via respective first and second port units and implemented using memory cells different from the DRAM cells implementing the first and second dedicated memory areas, and a port connection control unit controlling data path configuration between the shared memory area and the first and second port units to enable data communication between the first and second processors through the shared memory area.

摘要翻译： 多端口半导体存储器件包括： 分别耦合到第一和第二处理器的第一和第二端口单元，分别由第一和第二处理器访问的第一和第二专用存储器区域，并且使用DRAM单元实现;第一和第二处理器通过相应的第一和第二处理器共同访问的共享存储器区域 端口单元，并且使用与实现第一和第二专用存储区域的DRAM单元不同的存储器单元来实现，以及端口连接控制单元，其控制共享存储区域与第一和第二端口单元之间的数据路径配置，以使得第一 和第二个处理器通过共享内存区域。