公开(公告)号：US08767897B2

公开(公告)日：2014-07-01

申请号：US12905881

申请日：2010-10-15

申请人： Kung-Piao Huang

发明人： Kung-Piao Huang

IPC分类号： H04L7/00

CPC分类号： H04L7/0004

摘要： A method for timing error detection decision lock includes the following steps. Multiple detected values are obtained from a transmission signal. A moving sum mean signal is obtained according to the detected values. The moving sum mean signal is sampled every second constant period to obtain multiple sampling values. Whether the transmission signal is in a timing-lock status or an un-timing-lock status is determined according to relative relationships between the sampling values.

摘要翻译： 定时错误检测决定锁定的方法包括以下步骤。 从发送信号获得多个检测值。 根据检测值获得移动和平均信号。 移动和平均信号每隔一个恒定周期采样，得到多个采样值。 根据采样值之间的相对关系来确定发送信号是处于定时锁定状态还是非定时锁定状态。

公开(公告)号：US08369815B2

公开(公告)日：2013-02-05

申请号：US12912845

申请日：2010-10-27

申请人： Kung-Piao Huang

发明人： Kung-Piao Huang

IPC分类号： H04B1/10 ,  H04B17/00

CPC分类号： H04B17/345 ,  H04N17/04

摘要： A method for spectrum noise detection is provided. Means and a total mean of spectrum blocks of a frequency-domain signal are calculated. Whether the means are greater than a cut-off threshold is checked. If all the means are greater than the cut-off threshold, whether the means range between a variance lower bound and a variance upper bound is checked, an estimation bandwidth corresponding to the spectrum blocks is obtained according to a bandwidth check threshold, and whether a central frequency of the estimation bandwidth approximates a central frequency of the spectrum of the frequency-domain signal is checked. If the number of the means ranging between the variance lower bound and the variance upper bound exceeds a default value, and the estimation bandwidth is greater than a predetermined bandwidth and the central frequency of the estimation bandwidth approximates the central frequency, the frequency-domain signal is determined as a noise signal.

摘要翻译： 提供了一种用于频谱噪声检测的方法。 计算频域信号的频谱块的均值和总平均值。 检查装置是否大于截止阈值。 如果所有装置都大于截止阈值，则是否检查方差下限和方差上限之间的均值范围，则根据带宽检查阈值获得对应于频谱块的估计带宽，以及是否 估计带宽的中心频率近似于频域信号频谱的中心频率。 如果在方差下限与方差上限之间的平均值的数量超过默认值，并且估计带宽大于预定带宽，并且估计带宽的中心频率近似于中心频率，则频域信号 被确定为噪声信号。

公开(公告)号：US08924450B2

公开(公告)日：2014-12-30

申请号：US13028191

申请日：2011-02-15

申请人： Kung-Piao Huang

发明人： Kung-Piao Huang

IPC分类号： G06F17/10 ,  H03H17/02 ,  H03H17/06

CPC分类号： H03H17/0292 ,  H03H17/0664 ,  H03H2218/04 ,  H03H2220/04

摘要： A time-division (TD) decimation filter bank includes two decimation filter units. The first decimation filter unit operates at a system clock and receives a first-stage input data string. Each data in the first-stage input data string has a first part data and second part data. During the odd clock periods, the first part data are filtered and decimated in frequency. During the even clock periods, the second part data are filtered and decimated in frequency. The second decimation filter unit operates at the system clock and 2N clock periods are set as an operation-period unit, N≧2. The second decimation filter unit receives the outputs from the first decimation filter unit and receives several feedback data of the second decimation filter unit by TD, so that the received data are distributed into the 2N clock periods for filtering and decimation and outputting by TD.

摘要翻译： 时分（TD）抽取滤波器组包括两个抽取滤波器单元。 第一抽取滤波器单元在系统时钟下操作并接收第一级输入数据串。 第一级输入数据串中的每个数据具有第一部分数据和第二部分数据。 在奇数时钟周期期间，第一部分数据被滤波并抽取频率。 在偶数时钟周期期间，第二部分数据被频谱滤波和抽取。 第二抽取滤波器单元在系统时钟下操作，并且将2N个时钟周期设置为操作周期单元，N≥2。 第二抽取滤波器单元接收来自第一抽取滤波器单元的输出，并且通过TD接收第二抽取滤波器单元的若干反馈数据，使得接收的数据被分配到2N个时钟周期中，用于通过TD进行滤波和抽取和输出。

公开(公告)号：US20110151801A1

公开(公告)日：2011-06-23

申请号：US12912845

申请日：2010-10-27

申请人： Kung-Piao HUANG

发明人： Kung-Piao HUANG

IPC分类号： H04B17/00

CPC分类号： H04B17/345 ,  H04N17/04

摘要： A method for spectrum noise detection is provided. Means and a total mean of spectrum blocks of a frequency-domain signal are calculated. Whether the means are greater than a cut-off threshold is checked. If all the means are greater than the cut-off threshold, whether the means range between a variance lower bound and a variance upper bound is checked, an estimation bandwidth corresponding to the spectrum blocks is obtained according to a bandwidth check threshold, and whether a central frequency of the estimation bandwidth approximates a central frequency of the spectrum of the frequency-domain signal is checked. If the number of the means ranging between the variance lower bound and the variance upper bound exceeds a default value, and the estimation bandwidth is greater than a predetermined bandwidth and the central frequency of the estimation bandwidth approximates the central frequency, the frequency-domain signal is determined as a noise signal.

摘要翻译： 提供了一种用于频谱噪声检测的方法。 计算频域信号的频谱块的均值和总平均值。 检查装置是否大于截止阈值。 如果所有装置都大于截止阈值，则是否检查方差下限和方差上限之间的均值范围，则根据带宽检查阈值获得对应于频谱块的估计带宽，以及是否 估计带宽的中心频率近似于频域信号频谱的中心频率。 如果在方差下限与方差上限之间的平均值的数量超过默认值，并且估计带宽大于预定带宽，并且估计带宽的中心频率近似于中心频率，则频域信号 被确定为噪声信号。

公开(公告)号：US20110087716A1

公开(公告)日：2011-04-14

申请号：US12637771

申请日：2009-12-15

申请人： Kung-Piao Huang

发明人： Kung-Piao Huang

IPC分类号： G06F17/10

CPC分类号： H03H17/0294 ,  H03H17/0223 ,  H03H17/0621 ,  H03H2218/085

摘要： A multi-rate filter bank including an anti-aliasing filter, a plurality of multiplier block modules, a folding block, and a data composer is disclosed. The anti-aliasing filter receives an anti-aliasing input signal. The multiplier block modules receive an original signal and sequentially generate a plurality of processed signals. The multiplier block modules also receive a plurality of block input signals and a select signal. Each of the multiplier block modules is configured into a decimation block or an expanding anti-aliasing filter according to the select signal. The folding block receives the select signal and a folding input signal and generates a folding block output signal. The data composer receives and composes the folding block output signal and the outputs of the multiplexer block modules and the anti-aliasing filter and generates an anti-aliasing filter output signal.

摘要翻译： 公开了一种包括抗混叠滤波器，多个乘法器模块，折叠块和数据编辑器的多速率滤波器组。 抗混叠滤波器接收抗混叠输入信号。 乘法器模块模块接收原始信号并顺序产生多个处理的信号。 乘法器模块还接收多个块输入信号和选择信号。 每个乘法器块模块根据选择信号配置成抽取块或扩展抗混叠滤波器。 折叠块接收选择信号和折叠输入信号，并产生折叠块输出信号。 数据编辑器接收和组合折叠块输出信号和多路复用器模块和抗混叠滤波器的输出，并产生抗混叠滤波器输出信号。

公开(公告)号：US20110299643A1

公开(公告)日：2011-12-08

申请号：US12851564

申请日：2010-08-06

申请人： Kung-Piao Huang

发明人： Kung-Piao Huang

IPC分类号： H04L7/00

CPC分类号： H04L7/0337

摘要： A timing recovery controller capable of performing timing recovery for a data sequence at twice a symbol rate includes a sampler, a timing base device, a timing error detector and a timing lock detector. The timing error detector includes a first delay unit and a second delay unit, for delaying a data sequence to output a first delay data sequence and a second delay data sequence, respectively, and a timing error calculating module, for generating a timing error value, to adjust a time base. The timing lock detector includes a third delay unit, for delaying the data sequence to output a third delay data sequence, and a timing lock determination module, for generating a timing lock determination result.

摘要翻译： 能够以两倍的符号速率执行数据序列的定时恢复的定时恢复控制器包括采样器，定时基准装置，定时误差检测器和定时锁定检测器。 定时误差检测器包括第一延迟单元和第二延迟单元，用于分别延迟数据序列以输出第一延迟数据序列和第二延迟数据序列;以及定时误差计算模块，用于产生定时误差值， 调整时间基准。 定时锁定检测器包括用于延迟数据序列以输出第三延迟数据序列的第三延迟单元和用于产生定时锁定确定结果的定时锁定确定模块。

公开(公告)号：US20110133785A1

公开(公告)日：2011-06-09

申请号：US12905881

申请日：2010-10-15

申请人： Kung-Piao HUANG

发明人： Kung-Piao HUANG

IPC分类号： H03K5/153

CPC分类号： H04L7/0004

摘要： A method for timing error detection decision lock includes the following steps. Multiple detected values are obtained from a transmission signal. A moving sum mean signal is obtained according to the detected values. The moving sum mean signal is sampled every second constant period to obtain multiple sampling values. Whether the transmission signal is in a timing-lock status or an un-timing-lock status is determined according to relative relationships between the sampling values.

摘要翻译： 定时错误检测决定锁定的方法包括以下步骤。 从发送信号获得多个检测值。 根据检测值获得移动和平均信号。 移动和平均信号每隔一个恒定周期采样，得到多个采样值。 根据采样值之间的相对关系确定发送信号是处于定时锁定状态还是非定时锁定状态。

公开(公告)号：US08588355B2

公开(公告)日：2013-11-19

申请号：US12851564

申请日：2010-08-06

申请人： Kung-Piao Huang

发明人： Kung-Piao Huang

IPC分类号： H04L7/00 ,  H04L25/00 ,  H04L25/40

CPC分类号： H04L7/0337

摘要： A timing recovery controller capable of performing timing recovery for a data sequence at twice a symbol rate includes a sampler, a timing base device, a timing error detector and a timing lock detector. The timing error detector includes a first delay unit and a second delay unit, for delaying a data sequence to output a first delay data sequence and a second delay data sequence, respectively, and a timing error calculating module, for generating a timing error value, to adjust a time base. The timing lock detector includes a third delay unit, for delaying the data sequence to output a third delay data sequence, and a timing lock determination module, for generating a timing lock determination result.

摘要翻译： 能够以两倍的符号速率执行数据序列的定时恢复的定时恢复控制器包括采样器，定时基准装置，定时误差检测器和定时锁定检测器。 定时误差检测器包括第一延迟单元和第二延迟单元，用于分别延迟数据序列以输出第一延迟数据序列和第二延迟数据序列;以及定时误差计算模块，用于产生定时误差值， 调整时间基准。 定时锁定检测器包括用于延迟数据序列以输出第三延迟数据序列的第三延迟单元和用于产生定时锁定确定结果的定时锁定确定模块。

公开(公告)号：US08380772B2

公开(公告)日：2013-02-19

申请号：US12637771

申请日：2009-12-15

申请人： Kung-Piao Huang

发明人： Kung-Piao Huang

IPC分类号： G06F17/10

CPC分类号： H03H17/0294 ,  H03H17/0223 ,  H03H17/0621 ,  H03H2218/085

摘要： A multi-rate filter bank including an anti-aliasing filter, a plurality of multiplier block modules, a folding block, and a data composer is disclosed. The anti-aliasing filter receives an anti-aliasing input signal. The multiplier block modules receive an original signal and sequentially generate a plurality of processed signals. The multiplier block modules also receive a plurality of block input signals and a select signal. Each of the multiplier block modules is configured into a decimation block or an expanding anti-aliasing filter according to the select signal. The folding block receives the select signal and a folding input signal and generates a folding block output signal. The data composer receives and composes the folding block output signal and the outputs of the multiplexer block modules and the anti-aliasing filter and generates an anti-aliasing filter output signal.

摘要翻译： 公开了一种包括抗混叠滤波器，多个乘法器模块，折叠块和数据编辑器的多速率滤波器组。 抗混叠滤波器接收抗混叠输入信号。 乘法器模块模块接收原始信号并顺序产生多个处理的信号。 乘法器模块还接收多个块输入信号和选择信号。 每个乘法器块模块根据选择信号配置成抽取块或扩展抗混叠滤波器。 折叠块接收选择信号和折叠输入信号，并产生折叠块输出信号。 数据编辑器接收和组合折叠块输出信号和多路复用器模块和抗混叠滤波器的输出，并产生抗混叠滤波器输出信号。

公开(公告)号：US08744392B2

公开(公告)日：2014-06-03

申请号：US12871917

申请日：2010-08-31

申请人： Kung-Piao Huang

发明人： Kung-Piao Huang

IPC分类号： H04B1/06 ,  H04B7/00

CPC分类号： H03G3/3052

摘要： An automatic gain control method includes receiving a sequence of multiple digital data, and calculating a plurality of signal values corresponding to the respective voltage values of the digital data, such as multiple peak-to-peak voltage values or power values, so as to optimize a gain according to variations in the output values. The gain optimization includes updating a reference value according to the signal values. If the reference value is less than a minimum threshold, the gain is increased to cause the reference value to reach the minimum threshold. The gain optimization also includes analyzing a clipping rate according to the signal values. If the clipping rate is equal to zero, then the gain is adjusted up. If the clipping rate is greater than zero, then the gain is adjusted down, such that the clipping rate is decreased to approach to zero.

摘要翻译： 一种自动增益控制方法，包括接收多个数字数据的序列，并计算与数字数据的各个电压值对应的多个信号值，例如多个峰 - 峰值电压值或功率值，以便优化 根据输出值的变化增益。 增益优化包括根据信号值更新参考值。 如果参考值小于最小阈值，则增益增加以使参考值达到最小阈值。 增益优化还包括根据信号值分析限幅率。 如果削波率等于零，则增益被调整。 如果削波率大于零，则增益被调低，使得削波率降低到零。