公开(公告)号：US20050090071A1

公开(公告)日：2005-04-28

申请号：US10695193

申请日：2003-10-28

Applicant: Joseph Dower ,  Kultaransingh Hooghan

Inventor： Joseph Dower ,  Kultaransingh Hooghan

IPC: H01L21/70 ,  H01L21/76 ,  H01L23/544

CPC classification number: H01L23/544 ,  H01L2223/5442 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor chip and method of fabrication which permits precise location of hidden areas of the chip. At least two alignment marks are formed in or on the top passivation layer to provide topological features for location of the hidden areas. The hidden areas can then be selectively etched and/or added to, for example, by a focused ion beam for repair or other functions.

公开(公告)号：US20060028340A1

公开(公告)日：2006-02-09

申请号：US10911176

申请日：2004-08-04

Applicant: Kultaransingh Hooghan ,  James Cargo ,  Charles Berthoud ,  Scott McLellan ,  Kouros Azimi

Inventor： Kultaransingh Hooghan ,  James Cargo ,  Charles Berthoud ,  Scott McLellan ,  Kouros Azimi

IPC: G08B13/26

CPC classification number: H01L23/576 ,  H01L2924/0002 ,  Y10S257/922 ,  H01L2924/00

Abstract: The present invention provides an apparatus and method for detecting if a person has attempted to tamper with an integrated circuit (IC). The apparatus is located on the IC and comprises detection circuitry that detects a build up of electrical charge on the IC and disablement circuitry that disables the IC when the detection circuitry detects a build up of electrical charge on the IC. The method comprises detecting if a build up of electrical charge on the IC has occurred and disabling the IC when a build up of electrical charge on the IC has been detected.

Abstract translation: 本发明提供一种用于检测人是否试图篡改集成电路（IC）的装置和方法。 该装置位于IC上，并且包括检测电路，其检测IC上的电荷积累以及当检测电路检测到IC上的电荷累积时禁用IC的禁用电路。 该方法包括检测IC上的电荷积聚是否已经发生，并且当检测到IC上的电荷累积时禁止IC。

公开(公告)号：US20060068218A1

公开(公告)日：2006-03-30

申请号：US10951430

申请日：2004-09-28

Applicant: Kultaransingh Hooghan ,  John Osenbach ,  Brian Potteiger ,  Poopa Ruengsinsub ,  Richard Shook ,  Prakash Suratkar ,  Brian Vaccaro

Inventor： Kultaransingh Hooghan ,  John Osenbach ,  Brian Potteiger ,  Poopa Ruengsinsub ,  Richard Shook ,  Prakash Suratkar ,  Brian Vaccaro

IPC: B32B15/00 ,  B32B15/01

CPC classification number: C22C13/00 ,  B32B15/01 ,  C23C26/02 ,  H05K3/244 ,  H05K3/3463 ,  Y10S428/929 ,  Y10S428/941 ,  Y10T29/49121 ,  Y10T428/12493 ,  Y10T428/12708 ,  Y10T428/12715 ,  Y10T428/12722

Abstract: The electrical and mechanical properties of structures such as lead frames and other electrical/electronic devices containing, during processing, copper/tin interfaces are improved by introduction of nickel to such interface. Typically, a weight percentage of nickel to tin in the range 1 to 12 weight percent yields upon melting of the tin, an intermetallic compound with essentially no occluded, unbound tin. Thus undesirable anomalous structures such as tin needles and substantially non-planar interface compositions are avoided. Advantageously a nickel/tin/copper intermetallic interface that is substantially planar is formed in the substantial absence of needle-like tin structures.

Abstract translation: 通过在这种界面上引入镍来改善在加工期间包含铜/锡界面的诸如引线框架和其它电气/电子设备的结构的电和机械性能。 通常，锡至锡的重量百分比在1至12重量％范围内，其熔点为锡，金属间化合物基本上没有封闭的未结合的锡。 因此避免了不期望的异常结构，例如锡针和基本上非平面的界面组合物。 有利地，基本上没有针状锡结构形成基本上平坦的镍/锡/铜金属间界面。