公开(公告)号：US06496953B1

公开(公告)日：2002-12-17

申请号：US09526407

申请日：2000-03-15

Applicant: Joseph C. Helland

Inventor： Joseph C. Helland

IPC: G06F1100

CPC classification number: G01R31/3191 ,  G01R31/31921

Abstract: A method and apparata for correcting for pulse width timing error during testing of an integrated circuit are described. The method includes storing in a memory, associated with a selected terminal of an integrated circuit, event timing data pertaining to testing of the integrated circuit. Functional data is provided, pertaining to the testing, and it is determined if the functional data causes a state transition in the integrated circuit, the state transition causing a pulse. If a pulse is created, then the event timing data is adjusted, thereby to produce pulse width adjusted event timing. A test signal is then applied to the selected terminal of the integrated circuit, the test signal including pulse width adjusted event timing. A test program first loads scrambler and sequencer memories with a code representing event timing data and event type data for a number of events that are to occur during a test vector, as specified by the user. According to one embodiment, to implement single value pulse width calibration, additional coding is provided that reflects variations on event timing values compensating for pulse width timing error. Circuitry external to the local event sequencer of the tester analyzes the stream of functional data describing event polarity during every test cycle, and determines if a given bit of functional data ends a “short” pulse. The results of this analysis become part of the data stored in the scrambler memory. These data act as a pointer to select the address in the sequencer memory that contains the correct pulse width adjusted event timing data. According to another embodiment which implements general pulse width calibration, the event sequencer is modified to include pulse width calculation circuitry, which stores event time and event type data for the most recent events and calculates the pulse width of the present event by subtracting the nominal time value of the most recent event of the opposite polarity from the nominal time value of the present event. This pulse width value addresses a lookup table, which provides a corresponding calibration factor, to create pulse width adjusted event timing.

公开(公告)号：US06492797B1

公开(公告)日：2002-12-10

申请号：US09514708

申请日：2000-02-28

Applicant: Howard M. Maassen ,  William A. Fritzsche ,  Thomas P. Ho ,  Joseph C. Helland

Inventor： Howard M. Maassen ,  William A. Fritzsche ,  Thomas P. Ho ,  Joseph C. Helland

IPC: G01R1132

CPC classification number: G01R31/31905 ,  G01R31/3191 ,  G01R35/005

Abstract: A method and apparatus for calibrating tester timing accuracy during testing of integrated circuits. An ATE tester measures itself through reference blocks that have the same relevant dimensions as the integrated circuits to be tested. The number of reference blocks required is equal to the number of signal terminals on an integrated circuit to be tested being subject to timing calibration. A signal trace electrically connects a different signal terminal to a common reference terminal on each reference block. Each signal trace used should be closely matched both physically and electrically to the other signal traces used in the set of reference blocks, so that the electrical path length associated with each trace is nearly identical. To perform the timing calibration, the reference blocks may be mounted on a single fixture one at a time, or using multi-site fixtures, multiple reference blocks may be used in parallel. The fixture provides electrical connection of the reference block to the loadboard, and ultimately, the tester.

Abstract translation: 一种在集成电路测试期间校准测试仪定时精度的方法和装置。 ATE测试仪通过与要测试的集成电路具有相同尺寸的参考块来测量自身。 所需的参考块的数量等于要进行定时校准的待测试集成电路上的信号端子数。 信号迹线将不同的信号端子电连接到每个参考块上的公共参考端子。 所使用的每个信号迹线应该在物理和电气上与在该组参考块中使用的其它信号迹线紧密匹配，使得与每个迹线相关联的电路径长度几乎相同。 为了执行定时校准，参考块可以一次一个地安装在单个固定器上，或者使用多位置固定装置，可以并行使用多个参考块。 该夹具提供参考块与装载板的电连接，最终提供测试仪。