公开(公告)号：US09355615B2

公开(公告)日：2016-05-31

申请号：US14451029

申请日：2014-08-04

申请人： Jong-Ho Roh ,  Jae-Sop Kong

发明人： Jong-Ho Roh ,  Jae-Sop Kong

IPC分类号： G09G5/12 ,  G06F3/147 ,  G09G5/00

CPC分类号： G09G5/12 ,  G06F3/147 ,  G09G5/005 ,  G09G2330/021 ,  G09G2340/02 ,  G09G2340/0435 ,  G09G2360/18 ,  G09G2370/04

摘要： In one embodiment, the converter is configured to receive a first sync signal from a display driver and to convert the first sync signal into a second sync signal. The second sync signal is for controlling image sensing.

摘要翻译： 在一个实施例中，转换器被配置为从显示驱动器接收第一同步信号并将第一同步信号转换为第二同步信号。 第二同步信号用于控制图像感测。

公开(公告)号：US09066078B2

公开(公告)日：2015-06-23

申请号：US13617339

申请日：2012-09-14

申请人： Sung Chul Yoon ,  Jong Ho Roh

发明人： Sung Chul Yoon ,  Jong Ho Roh

IPC分类号： H04N13/00

CPC分类号： H04N13/139 ,  H04N2213/007

摘要： A display controller includes a merger and an alpha blender. The merger is configured to mix a first left frame including first left pixel data and a first right frame including first right pixel data based on a three-dimensional (3D) display format, and further configured and to output a first mixed frame and a second mixed frame. The alpha blender is configured to blend the first mixed frame and the second mixed frame to produce a first blended frame.

摘要翻译： 显示控制器包括合并器和α混合器。 合并被配置为基于三维（3D）显示格式混合包括第一左像素数据的第一左帧和包括第一右像素数据的第一右帧，并进一步配置并输出第一混合帧和第二混合帧 混合框架 α混合器配置成混合第一混合框架和第二混合框架以产生第一混合框架。

公开(公告)号：US08786637B2

公开(公告)日：2014-07-22

申请号：US13426796

申请日：2012-03-22

申请人： Min-Woo Song ,  Jong Ho Roh ,  Byoung Jin Ahn ,  Ho June Leu

发明人： Min-Woo Song ,  Jong Ho Roh ,  Byoung Jin Ahn ,  Ho June Leu

IPC分类号： G06T5/00

CPC分类号： G09G5/373 ,  G09G5/026 ,  G09G2340/0407

摘要： A scaler is provided and includes filters each receiving input pixel data and scaling the input pixel data using a scaling factor to generate a scaled pixel value, and a plurality of mixers, less than the plurality of filters. A first mixer performs a first blending operation on a first scaled pixel value and a second scaled pixel value provided by different filters. A second mixer performs a second blending operation on the blended result of the first mixer and a third scaled pixel value provided by anther filter.

摘要翻译： 提供了一种缩放器，并且包括各自接收输入像素数据并使用缩放因子缩放输入像素数据以生成缩放像素值的滤波器以及小于多个滤波器的多个混频器的滤波器。 第一混频器对由不同滤波器提供的第一缩放像素值和第二缩放像素值执行第一混合操作。 第二混频器对第一混频器的混合结果和由另一滤波器提供的第三缩放像素值执行第二混合操作。

公开(公告)号：US08713233B2

公开(公告)日：2014-04-29

申请号：US13050405

申请日：2011-03-17

申请人： Joon-Woo Cho ,  Jong Ho Roh ,  Jae Geun Yun ,  Sung-Min Hong

发明人： Joon-Woo Cho ,  Jong Ho Roh ,  Jae Geun Yun ,  Sung-Min Hong

IPC分类号： G06F13/00

CPC分类号： G06F13/368 ,  G06F12/0607 ,  G06F13/4022

摘要： Provided are an interconnect, a bus system with interconnect, and bus system operating method. The bus system includes a master, slaves access by the master, and an interconnect. The interconnect connects the master with the slaves in response to selection bits identified in a master address provided by the master.

摘要翻译： 提供互连，具有互连的总线系统和总线系统操作方法。 总线系统包括主机，主机的从机访问和互连。 响应于由主机提供的主地址中标识的选择位，互连将主机与从机连接。

公开(公告)号：US08650388B2

公开(公告)日：2014-02-11

申请号：US13064200

申请日：2011-03-10

申请人： Jong-Ho Roh ,  Min-Soo Lim

发明人： Jong-Ho Roh ,  Min-Soo Lim

IPC分类号： G06F9/00

CPC分类号： G06F9/4405 ,  G06F15/177

摘要： Multi-processor systems and methods thereof are provided. In an example, the multi-processor system may include a boot memory including a plurality of boot codes, each of the plurality of boot codes configured to facilitate an initialization process at one of a plurality of intellectual property (IP) blocks, each of the plurality of IP blocks having shared access to the boot memory. In another example, the multi-processor system may receive, from a first processor, a request to provide one of a plurality of boot codes from a boot memory, the received request sent in response to a system initializing signal, may read the requested boot code from the boot memory and may transfer, from a second processor, the read boot code to the first processor.

摘要翻译： 提供了多处理器系统及其方法。 在一个示例中，多处理器系统可以包括引导存储器，其包括多个引导代码，所述多个引导代码中的每一个被配置为便于在多个知识产权（IP）块之一处的初始化处理， 多个IP块具有对引导存储器的共享访问。 在另一示例中，多处理器系统可以从第一处理器接收从引导存储器提供多个引导代码中的一个的请求，响应于系统初始化信号发送的接收到的请求可以读取所请求的引导 来自引导存储器的代码，并且可以从第二处理器将读取引导代码传送到第一处理器。

公开(公告)号：US08319785B2

公开(公告)日：2012-11-27

申请号：US12072552

申请日：2008-02-27

申请人： Jong-Ho Roh

发明人： Jong-Ho Roh

IPC分类号： G06F12/00 ,  G09G5/39

CPC分类号： G09G5/397 ,  G09G5/393 ,  G09G5/395 ,  G09G2320/02

摘要： An image display system includes: a frame buffer including plurality of lines; a memory controller conducting writing and reading operations with the frame buffer; an image data provider supplying image data to the memory controller and generating a writing address; a display controller generating a reading address and receiving image data that is read from the frame buffer by the memory controller; a tearing-protection bus arbiter storing a burst length, receiving the writing and reading addresses, and selectively outputting the writing and reading addresses; and a display device displaying the image data by the display controller. The reading address contains a start address for the reading operation and the writing address contains a start address for the writing operation. If the writing and reading addresses are the same or if a difference between the start addresses for the writing and reading operations is less than the burst length, the tearing-protection bus arbiter outputs the reading address to the memory controller and holds the writing address.

摘要翻译： 一种图像显示系统，包括：包括多行的帧缓冲器; 存储器控制器，用帧缓冲器进行写入和读取操作; 图像数据提供者向存储器控制器提供图像数据并产生写入地址; 显示控制器，其生成读取地址并接收由所述存储器控制器从所述帧缓冲器读取的图像数据; 存储突发长度的撕裂保护总线仲裁器，接收写入和读取地址，并且选择性地输出写入和读取地址; 以及通过显示控制器显示图像数据的显示装置。 读取地址包含读取操作的起始地址，写入地址包含写入操作的起始地址。 如果写入和读取地址相同或写入和读取操作的起始地址之间的差异小于突发长度，则撕裂保护总线仲裁器将读取地址输出到存储器控制器并保持写入地址。

公开(公告)号：US20110102465A1

公开(公告)日：2011-05-05

申请号：US12908465

申请日：2010-10-20

申请人： Sung Jin Cho ,  Jong Ho Roh

发明人： Sung Jin Cho ,  Jong Ho Roh

IPC分类号： G09G5/00

CPC分类号： G06T1/60

摘要： An image processor includes a rotation block and a scaler which share a line buffer block with each other. The image processor receives rearranged pixel data from a memory unit based on rotation information for generating a rotated image and performs scaling on the rearranged pixel data.

摘要翻译： 图像处理器包括彼此共享行缓冲块的旋转块和缩放器。 图像处理器基于用于生成旋转图像的旋转信息从存储器单元接收重新排列的像素数据，并对重新排列的像素数据执行缩放。

公开(公告)号：US08963798B2

公开(公告)日：2015-02-24

申请号：US13028491

申请日：2011-02-16

申请人： Dong Han Lee ,  Jong Ho Roh

发明人： Dong Han Lee ,  Jong Ho Roh

IPC分类号： G09G5/12 ,  G06F3/14

CPC分类号： G06F3/1438 ,  G06F3/1446 ,  G09G5/12

摘要： The display controller includes a decoder, a control circuit, and a video output logic circuit. The decoder is configured to decode a first display command and output a decoding signal and first synchronizing information indicating the first display command is received. The control circuit is configured to generate a first control signal based on second synchronizing information and the decoding signal. The second synchronizing information is output from a second display controller and indicates a second display command is received. The video output logic circuit is configured to send a part of video data stored in a video source and a plurality of first timing control signals for displaying the part of the video data on a display to the display based on the first control signal.

摘要翻译： 显示控制器包括解码器，控制电路和视频输出逻辑电路。 解码器被配置为对第一显示命令进行解码并输出解码信号，并且接收到表示第一显示命令的第一同步信息。 控制电路被配置为基于第二同步信息和解码信号产生第一控制信号。 从第二显示控制器输出第二同步信息，并指示接收到第二显示命令。 视频输出逻辑电路被配置为发送存储在视频源中的视频数据的一部分和多个第一定时控制信号，用于基于第一控制信号将显示器上的视频数据的一部分显示在显示器上。

公开(公告)号：US08477144B2

公开(公告)日：2013-07-02

申请号：US12038476

申请日：2008-02-27

申请人： Jong-Ho Roh

发明人： Jong-Ho Roh

IPC分类号： G09G5/36 ,  G09G5/39

CPC分类号： G09G5/395

摘要： An image display system includes: a frame buffer having a plurality of lines, each of which stores image data and repetition information of the image data; a memory controller in signal communication with the frame buffer for reading the image data and the repetition information from the frame buffer; a display controller in signal communication with the memory controller for regenerating the image data, which is provided from the memory controller, in accordance with the repetition information provided from the memory controller; and a display device in signal communication with the display controller for displaying the regenerated image data, which is provided from the display controller, under regulation by the display controller.

摘要翻译： 图像显示系统包括：具有多行的帧缓冲器，每个行存储图像数据和图像数据的重复信息; 与帧缓冲器进行信号通信的存储器控​​制器，用于从帧缓冲器读取图像数据和重复信息; 与存储器控制器进行信号通信的显示控制器，用于根据从存储器控制器提供的重复信息再现从存储器控制器提供的图像数据; 以及与显示控制器进行信号通信的显示装置，用于显示由显示控制器提供的再生图像数据，由显示控制器进行调节。

公开(公告)号：US20120075262A1

公开(公告)日：2012-03-29

申请号：US13206704

申请日：2011-08-10

申请人： Kyoung Man Kim ,  Jong Ho Roh ,  Jae Sop Kong

发明人： Kyoung Man Kim ,  Jong Ho Roh ,  Jae Sop Kong

IPC分类号： G09G5/00

CPC分类号： G09G5/363

摘要： An under-run compensation circuit is provided. The under-run compensation circuit is configured to receive a clock signal, data, and an under-run detection signal that indicates whether or not an under-run is occurring. The under-run compensation circuit is further configured to output the clock signal and the data when receiving the under-run detection signal that indicates that an under-run is not occurring. The under-run compensation circuit is additionally configured to output the clock signal and dummy data when receiving the under- run detection signal that indicates that an under-run is occurring.

摘要翻译： 提供欠运行补偿电路。 欠运行补偿电路被配置为接收指示是否发生欠运行的时钟信号，数据和欠运行检测信号。 欠运行补偿电路还被配置为当接收到指示未发生欠运行的欠运行检测信号时输出时钟信号和数据。 欠运行补偿电路还被配置为当接收到指示发生欠运行的欠运行检测信号时输出时钟信号和伪数据。