-
公开(公告)号：US08930636B2
公开(公告)日：2015-01-06
申请号：US13555048
申请日：2012-07-20
IPC分类号： G06F12/08
CPC分类号： G06F12/0837 , G06F12/0815
摘要： One embodiment sets forth a technique for ensuring relaxed coherency between different caches. Two different execution units may be configured to access different caches that may store one or more cache lines corresponding to the same memory address. During time periods between memory barrier instructions relaxed coherency is maintained between the different caches. More specifically, writes to a cache line in a first cache that corresponds to a particular memory address are not necessarily propagated to a cache line in a second cache before the second cache receives a read or write request that also corresponds to the particular memory address. Therefore, the first cache and the second are not necessarily coherent during time periods of relaxed coherency. Execution of a memory barrier instruction ensures that the different caches will be coherent before a new period of relaxed coherency begins.
摘要翻译： 一个实施例提出了一种确保不同缓存之间的轻松一致性的技术。 可以将两个不同的执行单元配置为访问可以存储对应于相同存储器地址的一个或多个高速缓存行的不同高速缓存。 在存储器屏障指令之间的时间段期间，在不同的高速缓存之间保持轻松的一致性。 更具体地，在第二高速缓存接收到也对应于特定存储器地址的读取或写入请求之前，对与特定存储器地址相对应的第一高速缓存中的高速缓存行的写入不一定被传播到第二高速缓存中的高速缓存行。 因此，第一缓存和第二缓存在松弛一致性的时间段期间不一定是相干的。 存储器障碍指令的执行确保在新的松弛一致性周期开始之前，不同的高速缓存将是相干的。
-
2.发明授权公开(公告)号：US06633297B2
公开(公告)日：2003-10-14
申请号：US09934282
申请日：2001-08-20
申请人： Joel James McCormack , Keith Istvan Farkas , Norman P. Jouppi , Larry Dean Seiler , Robert Stephen McNamara
发明人： Joel James McCormack , Keith Istvan Farkas , Norman P. Jouppi , Larry Dean Seiler , Robert Stephen McNamara
IPC分类号： G06T120
摘要： In a graphics pipeline, a rasterizer circuit generates fragments for an image having multiple surfaces that have been tessellated into primitive objects, such as triangles. First and second fragments are associated with the same pixel. A merge buffer merges the first fragment with the second fragment when the two fragments belong to the same tessellated surface, the first fragment's primitive is adjacent to the second fragment's primitive, both fragments face either toward or away from the viewer, and the first and second fragment are sufficiently similar that merging is unlikely to introduce visually objectionable artifacts. A frame buffer receives fragments from the merge buffer, stores the fragments, combines the fragments into pixels, and outputs the pixels to a display.
摘要翻译： 在图形管线中，光栅化器电路为具有多个表面的图像生成片段，该多个表面已经被细分为原始对象，例如三角形。 第一和第二片段与相同的像素相关联。 当两个片段属于相同的镶嵌表面时，合并缓冲区将第一片段与第二片段合并，第一片段的原始物与第二片段的原始图片相邻，两个片段面向或远离观看者，并且第一和第二片段 片段足够相似，因此合并不太可能引起视觉上令人反感的伪像。 帧缓冲器从合并缓冲区接收片段，存储片段，将片段组合成像素，并将像素输出到显示器。
-
3.发明授权Hierarchical ring buffers for buffering data between processor and I/O device permitting data writes by processor and data reads by I/O device simultaneously directed at different buffers at different levels 失效用于在处理器和I / O设备之间缓冲数据的分层环形缓冲器，允许处理器进行数据写入和I / O设备的数据读取，同时针对不同级别的不同缓冲器
公开(公告)号：US06112267A
公开(公告)日：2000-08-29
申请号：US86134
申请日：1998-05-28
申请人： Joel James McCormack , Christopher Charles Gianos , James Timothy Claffey , Danny Paul Eggleston , Tracey L. Gustafson
发明人： Joel James McCormack , Christopher Charles Gianos , James Timothy Claffey , Danny Paul Eggleston , Tracey L. Gustafson
摘要： The invention includes an apparatus and method for buffering data transmitted by a processor and received by an I/O device via a memory and buses. The memory arranged at a plurality of levels includes a lower level of the memory operating faster than a higher level of the memory. A plurality of ring buffers are allocated at different levels of the memory and available buffers at a lowest possible level of the memory are preferentially selected as write buffers to store data transmitted by the processor. The apparatus includes a first level of the memory arranged on an integrated circuit with the processor, a second level of the memory arranged in an off-chip cache, and a third level of the memory arranged in a dynamic random access memory. Read buffers are selected to store data to be received by the I/O device. Stored control values indicate the order for selecting the read buffers and are used by the processor to select the write buffer. Control values are stored in sets of registers located in the I/O device and in a software-based set of registers located in the dynamic random access memory. A selection register located in the I/O device indicates the selected read buffer.
摘要翻译： 本发明包括一种用于缓冲由处理器发送并经由存储器和总线由I / O设备接收的数据的装置和方法。 布置在多个级别的存储器包括比存储器的较高级别快的存储器的较低级别。 在存储器的不同级别分配多个环形缓冲器，优选地将存储器的最低可能级别的可用缓冲器选择为写入缓冲器来存储由处理器发送的数据。 该装置包括布置在与处理器的集成电路上的存储器的第一级，布置在片外高速缓存中的存储器的第二级和布置在动态随机存取存储器中的存储器的第三级。 选择读缓冲区以存储要由I / O设备接收的数据。 存储的控制值指示选择读取缓冲区的顺序，并由处理器用于选择写入缓冲区。 控制值存储在位于I / O设备和位于动态随机存取存储器中的基于软件的寄存器组中的寄存器集合中。 位于I / O设备中的选择寄存器指示所选择的读缓冲区。
-
公开(公告)号：US20140025891A1
公开(公告)日：2014-01-23
申请号：US13555048
申请日：2012-07-20
IPC分类号： G06F12/08
CPC分类号： G06F12/0837 , G06F12/0815
摘要： One embodiment sets forth a technique for ensuring relaxed coherency between different caches. Two different execution units may be configured to access different caches that may store one or more cache lines corresponding to the same memory address. During time periods between memory barrier instructions relaxed coherency is maintained between the different caches. More specifically, writes to a cache line in a first cache that corresponds to a particular memory address are not necessarily propagated to a cache line in a second cache before the second cache receives a read or write request that also corresponds to the particular memory address. Therefore, the first cache and the second are not necessarily coherent during time periods of relaxed coherency. Execution of a memory barrier instruction ensures that the different caches will be coherent before a new period of relaxed coherency begins.
摘要翻译： 一个实施例提出了一种确保不同缓存之间的轻松一致性的技术。 可以将两个不同的执行单元配置为访问可以存储对应于相同存储器地址的一个或多个高速缓存行的不同高速缓存。 在存储器屏障指令之间的时间段期间，在不同的高速缓存之间保持轻松的一致性。 更具体地，在第二高速缓存接收到也对应于特定存储器地址的读取或写入请求之前，对与特定存储器地址相对应的第一高速缓存中的高速缓存行的写入不一定被传播到第二高速缓存中的高速缓存行。 因此，第一缓存和第二缓存在松弛一致性的时间段期间不一定是相干的。 存储器屏障指令的执行确保在新的松弛一致性周期开始之前，不同的高速缓存将是相干的。
-
5.发明授权Efficient hardware A-buffer using three-dimensional allocation of fragment memory 失效高效的硬件A缓冲区使用片段内存的三维分配公开(公告)号：US07336283B2
公开(公告)日：2008-02-26
申请号：US10280721
申请日：2002-10-24
IPC分类号： G06F12/02
CPC分类号： G09G5/363 , G06F12/0215 , G06F12/023 , G06T1/60 , G09G5/39
摘要： A method and apparatus for arranging fragments in a graphics memory. Each pixel of a display has a corresponding list of fragments in the graphics memory. Each fragment describes a three-dimensional surface at a plurality of sample points associated with the pixel. A predetermined number of fragments are statically allocated to each pixel. Additional space for fragment data is dynamically allocated and deallocated. Each dynamically allocated unit of memory contains fragment data for a plurality of pixels. Fragment data are arranged to exploit modem DRAM capabilities by increasing locality of reference within a single DRAM page, by putting other fragments likely to be referenced soon in pages that belong to non-conflicting banks, and by maintaining bookkeeping structures that allow the relevant DRAM precharge and row activate operations to be scheduled far in advance of access to fragment data.
摘要翻译： 一种用于在图形存储器中排列片段的方法和装置。 显示器的每个像素在图形存储器中具有相应的碎片列表。 每个片段描述与像素相关联的多个采样点处的三维表面。 将预定数量的片段静态分配给每个像素。 片段数据的附加空间被动态分配和释放。 每个动态分配的存储单元包含多个像素的片段数据。 片段数据被安排为通过增加单个DRAM页面内的参考位置来利用现代DRAM能力，通过将其他可能在不冲突银行的页面中被引用的片段放置在可能的地方，并且通过维持允许相关DRAM预充电的记账结构 并且行激活操作在对分段数据的访问之前被安排得很远。
-
公开(公告)号：US07081903B2
公开(公告)日：2006-07-25
申请号：US10020729
申请日：2001-12-12
IPC分类号： G09G5/00
摘要： A method and apparatus for visiting all productive stamp positions for a two-dimensional convex polygonal object. The object is visited with a stamp that has a stamp rectangle, and one or more discrete sample points. A productive location is one for which the object contains at least one of the stamp's sample points when the stamp is placed at that location. An unproductive location is one for which the object contains none of the stamp's sample points when the stamp is placed at that location. Stamp locations are discrete points that are separated vertically by the stamp rectangle's height, and horizontally by the stamp rectangle's width. The stamp may move to a nearby position, or to a previously saved position, as it traverses the object. The stamp moves in such a way as to visit all productive locations for an object while avoiding most of the unproductive locations.
-
公开(公告)号：US06714196B2
公开(公告)日：2004-03-30
申请号：US09934236
申请日：2001-08-20
IPC分类号： G06T1500
CPC分类号： H04L67/36 , G06T11/40 , G09G5/393 , G09G2360/121 , G09G2360/122 , H04L69/329
摘要： A method and apparatus for visiting all stamps that are relevant to a two-dimensional convex polygonal object. The object is visited with a rectangular stamp, which contains one or more discrete sample points. A relevant location is one for which the object contains at least one of the stamp's sample points when the stamp is placed at that location. Stamp locations are discrete points that are separated vertically by the stamp's height, and horizontally by the stamp's width. The stamp may move to a nearby position, or to a previously saved position, as it traverses the object. The plane in which the object lies is partitioned into rectangular tiles, which are at least as wide and high as the stamp. The invention visits stamp locations in an order that respects tile boundaries—that is, it visits all locations within one tile before visiting any locations within another tile. The invention may also be used with further partitioning of the plane (metatiles), so that it will visit all locations within a metatile before visiting any locations within another metatile, and further visit all locations within a portion of a tile within the current metatile before visiting any locations within a portion of a different tile within the current metatile.
摘要翻译： 一种用于访问与二维凸多边形对象相关的所有邮票的方法和装置。 使用矩形邮票访问该对象，其中包含一个或多个离散的采样点。 相关的位置是当邮票放置在该位置时，对象包含至少一个邮票的采样点。 邮票位置是垂直分隔邮票高度，水平依印戳宽度的离散点。 邮票可以移动到附近的位置，或移动到先前保存的位置，当它穿过物体。 物体所在的平面被划分成矩形瓦片，其至少与印章一样宽和高。 本发明按照尊重瓦片边界的顺序来访问印记位置，即，在访问另一瓦片内的任何位置之前访问一个瓦片内的所有位置。 本发明还可以与平面（偏差）的进一步划分一起使用，以便在访问另一容器内的任何位置之前，它将访问易于使用的所有位置，并且进一步访问当前易于使用的瓦片的一部分内的所有位置 访问当前可使用的不同瓦片的一部分内的任何位置。
-
-
-
-
-
-
搜索结果
7 条记录 (耗时 0.018 秒)
