Abstract:
Disclosed is a level shifter that includes an input node; first and second voltage shifter circuits configured to generate an output clock of a second voltage domain in response to an input clock of a first voltage domain input via the input node, and an output node configured to output the output clock, wherein the first and second voltage shifter circuits have the same structure and are connected in parallel between the input node and an output node.
Abstract:
Disclosed is a level shifter that includes an input node; first and second voltage shifter circuits configured to generate an output clock of a second voltage domain in response to an input clock of a first voltage domain input via the input node, and an output node configured to output the output clock, wherein the first and second voltage shifter circuits have the same structure and are connected in parallel between the input node and an output node.