Method of compressing lookup table for reducing memory, non-linear function generating apparatus having lookup table compressed using the method, and non-linear function generating method
    1.
    发明授权
    Method of compressing lookup table for reducing memory, non-linear function generating apparatus having lookup table compressed using the method, and non-linear function generating method 失效
    用于缩小存储器的查找表的方法,具有使用该方法压缩的查找表的非线性函数生成装置以及非线性函数生成方法

    公开(公告)号:US06900747B2

    公开(公告)日:2005-05-31

    申请号:US10685740

    申请日:2003-10-15

    申请人: Heon-soo Lee

    发明人: Heon-soo Lee

    CPC分类号: H03M7/30

    摘要: In a method of compressing a lookup table for reducing memory, a non-linear function generating apparatus having a lookup table compressed using the method, and a non-linear function generating method, X-coordinates of the non-linear function are separated into a plurality of sections including steps that have predetermined step sizes. Y-coordinate values corresponding to X-coordinate values are extracted for each step. The Y-coordinate values are stored in predetermined addresses in a memory, wherein the step sizes are different according to the sections. In this manner, memory capacity occupied by the lookup table is reduced.

    摘要翻译: 在压缩用于减少存储器的查找表的方法中,具有使用该方法压缩的查找表的非线性函数生成装置和非线性函数生成方法将非线性函数的X坐标分成 多个部分包括具有预定步长的步骤。 针对每个步骤提取与X坐标值对应的Y坐标值。 Y坐标值存储在存储器中的预定地址中,其中步长根据部分而不同。 以这种方式,减少查找表所占用的存储容量。

    Method and apparatus for providing platform independent secure domain
    4.
    发明申请
    Method and apparatus for providing platform independent secure domain 审中-公开
    提供平台独立安全域的方法和装置

    公开(公告)号:US20100293357A1

    公开(公告)日:2010-11-18

    申请号:US12662480

    申请日:2010-04-20

    IPC分类号: G06F9/38 G06F9/312 G06F12/00

    摘要: A platform independent secure domain providing apparatus, which determines whether an execution environment is to be in a secure domain and a non-secure domain by a secure bit. The apparatus includes a secure monitor that is adapted to generate a branch instruction when a call to a secure code is sensed, turn on the secure bit when the branch instruction has been successfully executed, and turn off the secure bit when the execution of the secure code is finished, an instruction bypass read only memory (ROM) adapted to receive the branch instruction from the secure monitor, and a processor adapted to execute the branch instruction that is fetched from the instruction bypass ROM.

    摘要翻译: 独立于平台的安全域提供装置,其确定执行环境是否位于安全域和非安全域中。 该装置包括安全监视器,适于在感测到对安全码的呼叫时产生分支指令,当分支指令已成功执行时打开安全位,并且当执行安全码时,关闭安全位 代码完成,适于从安全监视器接收转移指令的指令旁路只读存储器(ROM)以及适于执行从指令旁路ROM获取的分支指令的处理器。

    ENCRYPTOR/DECRYPTOR, ELECTRONIC DEVICE INCLUDING ENCRYPTOR/DECRYPTOR, AND METHOD OF OPERATING ENCRYPTOR/DECRYPTOR
    5.
    发明申请
    ENCRYPTOR/DECRYPTOR, ELECTRONIC DEVICE INCLUDING ENCRYPTOR/DECRYPTOR, AND METHOD OF OPERATING ENCRYPTOR/DECRYPTOR 有权
    加密器/解码器,包括加密器/解码器的电子设备,以及操作加密器/解码器的方法

    公开(公告)号:US20160112188A1

    公开(公告)日:2016-04-21

    申请号:US14790106

    申请日:2015-07-02

    IPC分类号: H04L9/06

    摘要: An encryptor/decryptor, an electronic device including the encryptor/decryptor, and a method of operating the encryptor/decryptor are provided. The method of operating the encryptor/decryptor includes distributing an input plaintext stream to a plurality of encryption/decryption cores by pieces of plaintext data; performing a first operation by a first encryption/decryption core from among the plurality of encryption/decryption cores; and encrypting the plaintext data to ciphertext data or decrypting the ciphertext data to the plaintext data by each of the plurality of encryption/decryption cores by using a result of performing the first operation in the first encryption/decryption core.

    摘要翻译: 提供了加密/解密器,包括加密器/解密器的电子设备以及操作加密器/解密器的方法。 操作加密/解密器的方法包括:通过明文数据片段将输入明文流分发到多个加密/解密核心; 通过所述多个加密/解密核中的第一加密/解密核执行第一操作; 以及通过使用在所述第一加密/解密核心中执行所述第一操作的结果,将所述明文数据加密为密文数据,或者通过所述多个加密/解密核心中的每一个将密文数据解密为明文数据。

    Duty cycle correction circuit
    7.
    发明申请
    Duty cycle correction circuit 审中-公开
    占空比校正电路

    公开(公告)号:US20060114042A1

    公开(公告)日:2006-06-01

    申请号:US11286686

    申请日:2005-11-23

    IPC分类号: H03K3/017

    CPC分类号: H03K5/1565 H03K5/086

    摘要: There is provided a compact duty cycle correction circuit including minimal components for generating a signal with a 50% duty cycle. The duty cycle correction circuit includes a storage element and a correction circuit. The storage element generates an output signal in response to a clock signal and a feedback signal. The correction circuit includes a resistor and a capacitor and outputs the feedback signal in response to the output signal of the storage element.

    摘要翻译: 提供了一种紧凑的占空比校正电路,其包括用于产生具有50%占空比的信号的最小组件。 占空比校正电路包括存储元件和校正电路。 存储元件响应于时钟信号和反馈信号产生输出信号。 校正电路包括电阻器和电容器,并且响应于存储元件的输出信号而输出反馈信号。

    ELECTRONIC SYSTEM HAVING INTEGRITY VERIFICATION DEVICE
    9.
    发明申请
    ELECTRONIC SYSTEM HAVING INTEGRITY VERIFICATION DEVICE 有权
    具有完整性验证装置的电子系统

    公开(公告)号:US20150254458A1

    公开(公告)日:2015-09-10

    申请号:US14638862

    申请日:2015-03-04

    IPC分类号: G06F21/57

    摘要: Provided are an electronic system, an integrity verification device, and a method of performing an integrity verification operation. The electronic system includes: a memory device; a processor configured to provide a plurality of configuration records corresponding to a plurality of verification data stored in the memory device, each of the configuration records including a start address, a data length, and a reference hash value for a corresponding verification data; and an integrity verification device configured to: store the configuration records, select a configuration record, directly access the memory device to read verification data, corresponding to the selected configuration record, based on the start address and the data length included in the selected configuration record, perform a hash operation on the verification data to obtain a verification hash value, and output an interrupt signal based on the verification hash value and the reference hash value comprised in the selected configuration record.

    摘要翻译: 提供电子系统,完整性验证装置和执行完整性验证操作的方法。 电子系统包括:存储装置; 处理器,其被配置为提供与存储在所述存储器件中的多个验证数据相对应的多个配置记录,所述配置记录包括相应验证数据的起始地址,数据长度和参考散列值; 以及完整性验证装置,被配置为:基于包括在所选配置记录中的开始地址和数据长度,存储配置记录,选择配置记录,直接访问存储设备以读取与所选配置记录相对应的验证数据 对验证数据执行哈希操作以获得验证散列值,并且基于所选配置记录中包含的验证散列值和参考散列值输出中断信号。

    ELECTRONIC DEVICE BOOTED UP WITH SECURITY, A HASH COMPUTING METHOD, AND A BOOT-UP METHOD THEREOF
    10.
    发明申请
    ELECTRONIC DEVICE BOOTED UP WITH SECURITY, A HASH COMPUTING METHOD, AND A BOOT-UP METHOD THEREOF 审中-公开
    具有安全性的电子设备,散列计算方法及其启动方法

    公开(公告)号:US20090144559A1

    公开(公告)日:2009-06-04

    申请号:US12249295

    申请日:2008-10-10

    IPC分类号: G06F21/00

    CPC分类号: G06F21/575

    摘要: A method for authenticating a public key to execute a process with security, including: invoking a process; reading a public key from a first source; calculating a hash value of the public key with a block encryption algorithm, wherein part of the public key is an initial input value of the block encryption algorithm; reading a hash value from a second source; comparing the calculated hash value to the read hash value to determine if the public key is authentic; and executing the process if the public key is authentic.

    摘要翻译: 一种用于认证公钥以执行具有安全性的过程的方法,包括:调用进程; 从第一个来源读取公钥; 使用块加密算法计算公钥的哈希值,其中公钥的一部分是块加密算法的初始输入值; 从第二个源读取哈希值; 将所计算的散列值与读取的散列值进行比较,以确定公钥是否是真实的; 并且如果公钥是真实的,则执行该过程。