公开(公告)号：US20050110096A1

公开(公告)日：2005-05-26

申请号：US10904565

申请日：2004-11-16

申请人： Arne Ballantine ,  Kevin Chan ,  Jeffrey Gilbert ,  Kevin Houlihan ,  Glen Miles ,  James Quinlivan ,  Samuel Ramac ,  Michael Rice ,  Beth Ward

发明人： Arne Ballantine ,  Kevin Chan ,  Jeffrey Gilbert ,  Kevin Houlihan ,  Glen Miles ,  James Quinlivan ,  Samuel Ramac ,  Michael Rice ,  Beth Ward

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/76 ,  H01L21/3205 ,  H01L21/4763 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/28035 ,  H01L29/4925 ,  H01L29/665

摘要： Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting CMOS transistor may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size may be directed to maximize dopant activation in the polysilicon near the gate dielectric and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. A region of polycrystalline silicon may have a varying grain size as a function of a distance measured from a surface of the dielectric film.

摘要翻译： 通过在受控条件下沉积多晶硅来减少多晶硅栅电极中的多晶硅电耗，从而通过多晶硅的厚度来改变晶粒尺寸。 所得到的CMOS晶体管可以具有各自的晶粒尺寸的两个或更多个深度连续的区域，并且可以针对晶体尺寸的选择来最大化在栅极电介质附近的多晶硅中的掺杂剂活化，并且将多晶硅的电阻调整到高于该 第一区域并且远离栅极电介质。 多晶硅的区域可以具有作为从电介质膜的表面测量的距离的函数的变化的晶粒尺寸。