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公开(公告)号：US08370787B2
公开(公告)日：2013-02-05
申请号：US12547382
申请日：2009-08-25
CPC分类号： H04L9/3278 , G06F21/577 , G09C1/00 , H04L2209/26
摘要： Methods, apparatuses and articles for testing security of a mapping function—such as a Physically Unclonable Function (PUF)—of an integrated circuit (IC) are disclosed. In various embodiments, one or more tests may be performed. In various embodiments, the tests may include a predictability test, a collision test, a sensitivity test, a reverse-engineering test and an emulation test. In various embodiments, a test may determine a metric to indicate a level of security or vulnerability. In various embodiments, a test may include characterizing one or more delay elements and/or path segments of the mapping function. Other embodiments may be described and claimed.
摘要翻译： 公开了用于测试集成电路（IC）的映射功能（例如物理不可克隆功能（PUF））的安全性的方法，装置和文章。 在各种实施例中，可以执行一个或多个测试。 在各种实施例中，测试可以包括可预测性测试，碰撞测试，灵敏度测试，逆向工程测试和仿真测试。 在各种实施例中，测试可以确定指示安全级别或漏洞级别的度量。 在各种实施例中，测试可以包括表征映射函数的一个或多个延迟元件和/或路径段。 可以描述和要求保护其他实施例。
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公开(公告)号：US08365131B2
公开(公告)日：2013-01-29
申请号：US12685114
申请日：2010-01-11
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F17/5054 , G06F2217/16
摘要： Technologies are generally described for hardware synthesis using thermally aware scheduling and binding. Multiple versions of a hardware design may be generated, each having variations of schedule and binding results. The scheduling and binding may be performed such that thermal profiles of the multiple versions have thermal peaks that are distant between the versions. The increased physical distance between the thermal peaks of the versions can give the versions unique thermal characteristics. A schedule of rotation between the multiple versions of the design may be constructed such that the thermal profile of the integrated circuit balances out during operation. A linear programming framework may be used to analyze the multiple designs and construct a thermally aware rotation scheduling and binding. For example, the K most efficient versions may be selected and then durations for operating each version within a rotation may be determined.
摘要翻译： 通常使用热感知调度和绑定来描述用于硬件合成的技术。 可以生成多个版本的硬件设计，每个版本具有日程表和绑定结果的变化。 可以执行调度和绑定，使得多个版本的热分布具有在这些版本之间较远的热峰。 这些版本的热峰之间物理距离的增加可以赋予版本独特的热特性。 可以构造设计的多个版本之间的旋转时间表，使得集成电路的热分布在操作期间平衡。 可以使用线性规划框架来分析多个设计并构建热感知旋转调度和绑定。 例如，可以选择K个最有效的版本，然后可以确定在旋转期间操作每个版本的持续时间。
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公开(公告)号：US08054098B2
公开(公告)日：2011-11-08
申请号：US12984275
申请日：2011-01-04
IPC分类号： H03K19/00
CPC分类号： H03K19/17768 , G06F21/72 , G06F2221/2105 , G06F2221/2153 , H04L9/3215 , H04L9/3278 , H04L2209/603 , H04L2209/805
摘要： Embodiments generally describe techniques for an integrated circuit having a physical unclonable function (PUF). Example integrated circuits may include an input circuit having an input network, a configurable delay circuit having one or more configurable delay chains, and an output circuit having one or more arbiters, serially coupled together. Each delay chain may include a number of serially coupled configurable switching-delay elements adapted to receive, configurably propagate, and output two delayed signals. Each delay chain may be configured using configuration signals responsively output by the input network in response to challenges provided to the input network. The output circuit may further include an output network to generate combined output signals based on the signals output by the arbiters. Each of the input and/or output networks may comprise combinatorial logic, sequential logic, or another PUF, which may be of the same design. Other embodiments may be disclosed and claimed.
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公开(公告)号：US07898283B1
公开(公告)日：2011-03-01
申请号：US12551209
申请日：2009-08-31
IPC分类号： H03K19/00
CPC分类号： H03K19/17768 , G06F21/72 , G06F2221/2105 , G06F2221/2153 , H04L9/3215 , H04L9/3278 , H04L2209/603 , H04L2209/805
摘要： Embodiments generally describe techniques for an integrated circuit having a physical unclonable function (PUF). Example integrated circuits may include an input circuit having an input network, a configurable delay circuit having one or more configurable delay chains, and an output circuit having one or more arbiters, serially coupled together. Each delay chain may include a number of serially coupled configurable switching-delay elements adapted to receive, configurably propagate, and output two delayed signals. Each delay chain may be configured using configuration signals responsively output by the input network in response to challenges provided to the input network. The output circuit may further include an output network to generate combined output signals based on the signals output by the arbiters. Each of the input and/or output networks may comprise combinatorial logic, sequential logic, or another PUF, which may be of the same design. Other embodiments may be disclosed and claimed.
摘要翻译： 实施例通常描述具有物理不可克隆功能（PUF）的集成电路的技术。 示例性集成电路可以包括具有输入网络的输入电路，具有一个或多个可配置延迟链的可配置延迟电路，以及具有串联耦合在一起的一个或多个仲裁器的输出电路。 每个延迟链可以包括适于接收，可配置地传播和输出两个延迟信号的多个串联耦合的可配置开关延迟元件。 可以响应于提供给输入网络的挑战，使用由输入网络响应地输出的配置信号来配置每个延迟链。 输出电路还可以包括输出网络，以基于由仲裁器输出的信号产生组合的输出信号。 输入和/或输出网络中的每一个可以包括组合逻辑，顺序逻辑或可以具有相同设计的另一PUF。 可以公开和要求保护其他实施例。
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公开(公告)号：US08732468B2
公开(公告)日：2014-05-20
申请号：US12720628
申请日：2010-03-09
IPC分类号： G06F21/00
摘要： Techniques are able to lock and unlock and integrated circuit (IC) based device by encrypting/decrypting a bus on the device. The bus may be a system bus for the IC, a bus within the IC, or an external input/output bus. A shared secret protocol is used between an IC designer and a fabrication facility building the IC. The IC at the fabrication facility scrambles the bus on the IC using an encryption key generated from unique identification data received from the IC designer. With the IC bus locked by the encryption key, only the IC designer may be able to determine and communicate the appropriate activation key required to unlock (e.g., unscramble) the bus and thus make the integrated circuit usable.
摘要翻译： 技术能够通过对设备上的总线进行加密/解密来锁定和解锁基于集成电路（IC）的设备。 总线可以是IC的系统总线，IC内的总线或外部输入/输出总线。 在IC设计人员和构建IC的制造设施之间使用共享秘密协议。 制造设备上的IC使用从IC设计者接收的唯一识别数据产生的加密密钥来加扰IC上的总线。 通过加密密钥锁定IC总线，只有IC设计者才能够确定和通信解锁（例如，解扰）总线所需的适当激活密钥，从而使集成电路可用。
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公开(公告)号：US20110055649A1
公开(公告)日：2011-03-03
申请号：US12547382
申请日：2009-08-25
IPC分类号： G06F11/267 , G01R31/28
CPC分类号： H04L9/3278 , G06F21/577 , G09C1/00 , H04L2209/26
摘要： Methods, apparatuses and articles for testing security of a mapping function—such as a Physically Unclonable Function (PUF)—of an integrated circuit (IC) are disclosed. In various embodiments, one or more tests may be performed. In various embodiments, the tests may include a predictability test, a collision test, a sensitivity test, a reverse-engineering test and an emulation test. In various embodiments, a test may determine a metric to indicate a level of security or vulnerability. In various embodiments, a test may include characterizing one or more delay elements and/or path segments of the mapping function. Other embodiments may be described and claimed.
摘要翻译： 公开了用于测试集成电路（IC）的映射功能（例如物理不可克隆功能（PUF））的安全性的方法，装置和文章。 在各种实施例中，可以执行一个或多个测试。 在各种实施例中，测试可以包括可预测性测试，碰撞测试，灵敏度测试，逆向工程测试和仿真测试。 在各种实施例中，测试可以确定指示安全级别或漏洞级别的度量。 在各种实施例中，测试可以包括表征映射函数的一个或多个延迟元件和/或路径段。 可以描述和要求保护其他实施例。
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公开(公告)号：US20100287604A1
公开(公告)日：2010-11-11
申请号：US12463984
申请日：2009-05-11
CPC分类号： G01R19/25 , G01R31/2851 , G06F15/00 , G06F21/73
摘要： Techniques are generally described for generating an identification number for an integrated circuit (IC). In some examples, methods for generating an identification of an IC may comprise selecting circuit elements of the IC, evaluating measurements of an attribute of the IC for the selected circuit elements, wherein individual measurements are associated with corresponding input vectors previously applied to the IC, solving a plurality of equations formulated based at least in part on the measurements taken of the attribute of the IC for the selected circuit elements to determine scaling factors for the selected circuit elements, and transforming the determined scaling factors for the selected circuit elements to generate an identification number of the IC. Additional variants and embodiments may also be disclosed.
摘要翻译： 通常描述用于产生集成电路（IC）的识别号码的技术。 在一些示例中，用于产生IC的标识的方法可以包括：选择IC的电路元件，评估用于所选择的电路元件的IC的属性的测量，其中各个测量与先前应用于IC的相应输入矢量相关联， 解决至少部分地基于针对所选择的电路元件的IC的属性的测量来确定所选择的电路元件的缩放因子并且变换所选择的电路元件的确定的缩放因子以产生 IC的识别号码。 还可以公开附加的变型和实施例。
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公开(公告)号：US20100287374A1
公开(公告)日：2010-11-11
申请号：US12720628
申请日：2010-03-09
IPC分类号： G06F21/00
摘要： Techniques are able to lock and unlock and integrated circuit (IC) based device by encrypting/decrypting a bus on the device. The bus may be a system bus for the IC, a bus within the IC, or an external input/output bus. A shared secret protocol is used between an IC designer and a fabrication facility building the IC. The IC at the fabrication facility scrambles the bus on the IC using an encryption key generated from unique identification data received from the IC designer. With the IC bus locked by the encryption key, only the IC designer may be able to determine and communicate the appropriate activation key required to unlock (e.g., unscramble) the bus and thus make the integrated circuit usable.
摘要翻译： 技术能够通过对设备上的总线进行加密/解密来锁定和解锁基于集成电路（IC）的设备。 总线可以是IC的系统总线，IC内的总线或外部输入/输出总线。 在IC设计人员和构建IC的制造设施之间使用共享秘密协议。 制造设备上的IC使用从IC设计者接收的唯一识别数据产生的加密密钥来加扰IC上的总线。 通过加密密钥锁定IC总线，只有IC设计者才能够确定和通信解锁（例如，解扰）总线所需的适当激活密钥，从而使集成电路可用。
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公开(公告)号：US08966660B2
公开(公告)日：2015-02-24
申请号：US12537978
申请日：2009-08-07
CPC分类号： G06F21/10
摘要： Methods for remote activation and permanent or temporary deactivation of integrated circuits (IC) for digital rights management are disclosed. Remote activation enables designers to remotely control each IC manufactured by an independent silicon foundry. Certain embodiments of the invention exploit inherent unclonable variability in modern manufacturing for the creation of unique identification (ID) and then integrate the IDs into the circuit functionality. Some of the objectives may be realized by replicating a subset of states of one or more finite state machines and by superimposing additional state transitions that are known only to the designer. On each chip, the added transitions signals are a function of the unique IDs and are thus unclonable. The method and system of the invention is robust against operational and environment conditions, unclonable and attack-resilient, while having a low overhead and a unique key for each IC with very high probability.
摘要翻译： 公开了用于数字权限管理的集成电路（IC）的远程激活和永久或临时停用的方法。 远程激活使设计人员能够远程控制独立硅晶圆厂商制造的每个IC。 本发明的某些实施例利用现代制造中固有的不可克隆的变异性来创建唯一标识（ID），然后将这些ID集成到电路功能中。 一些目标可以通过复制一个或多个有限状态机的状态的子集并且通过叠加仅对设计者已知的附加状态转换来实现。 在每个芯片上，添加的转换信号是唯一ID的函数，因此是不可克隆的。 本发明的方法和系统对于操作和环境条件是稳健的，不可克隆和具有攻击性，而对于每个IC具有低开销和独特的密钥，其概率非常高。
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10.发明授权公开(公告)号：US08443034B2
公开(公告)日：2013-05-14
申请号：US12479584
申请日：2009-06-05
IPC分类号： G01F31/31835 , H03H11/40
CPC分类号： G01R31/31835
摘要： Techniques are generally described for selecting input vectors that reduce or minimize leakage current for a plurality of integrated circuits (ICs) with the same design, but that differ due to manufacturing variability. In various embodiments, the techniques include determining at least one starting input vector that reduces leakage current in a respective one of N instances of the ICs, and selecting from the determined at least one starting input vector of each respective one of the N instances, a set R of representative input vectors. Some of the embodiments then use each of the representative input vectors in the set R to determine at least a particular input vector to apply to input terminals of an IC in the plurality of ICs to reduce or minimize leakage current in the IC. Additional variants and embodiments may also be disclosed.
摘要翻译： 通常描述技术用于选择减少或最小化具有相同设计的多个集成电路（IC）的漏电流的输入向量，但由于制造变异性而不同。 在各种实施例中，这些技术包括确定减少IC的N个实例中的相应一个中的泄漏电流的至少一个起始输入向量，并且从所确定的N个实例中的每个相应一个的起始输入向量中选择一个 设定代表性输入向量的R。 一些实施例然后使用集合R中的每个代表性输入向量来确定至少一个特定的输入向量，以施加到多个IC中的IC的输入端子，以减少或最小化IC中的漏电流。 还可以公开附加的变型和实施例。
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