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    Defect detection recipe definition
    1.
    发明授权
    Defect detection recipe definition 有权
    缺陷检测配方定义

    公开(公告)号：US08289508B2

    公开(公告)日：2012-10-16

    申请号：US12621510

    申请日：2009-11-19

    Applicant: Victor Seng Keong Lim ,  Rachel Yie Fang Wai ,  Fang Hong Gn ,  Liang Choo Hsia

    Inventor： Victor Seng Keong Lim ,  Rachel Yie Fang Wai ,  Fang Hong Gn ,  Liang Choo Hsia

    IPC: G01N21/00

    CPC classification number: H01L22/12

    Abstract: A method of forming a device is disclosed. The method includes providing a substrate and processing a layer of the device on the substrate. The layer is inspected with an inspection tool for defects. The inspection tool is programmed with an inspection recipe determined from studying defects programmed into the layer at known locations.

    Abstract translation: 公开了一种形成装置的方法。 该方法包括提供衬底并在衬底上处理器件的一层。 该层用检查工具检查缺陷。 检查工具用从在已知位置处编程到层中的缺陷来确定的检查配方来编程。

    Defect monitoring in semiconductor device fabrication
    3.
    发明授权
    Defect monitoring in semiconductor device fabrication 有权
    半导体器件制造中的缺陷监测

    公开(公告)号：US08339449B2

    公开(公告)日：2012-12-25

    申请号：US12537269

    申请日：2009-08-07

    Applicant: Barbara Fong Chin Lim ,  Keng Heng Lai ,  Tanya Yang ,  Victor Seng Keong Lim ,  Fang Hong Gn ,  Liang Choo Hsia

    Inventor： Barbara Fong Chin Lim ,  Keng Heng Lai ,  Tanya Yang ,  Victor Seng Keong Lim ,  Fang Hong Gn ,  Liang Choo Hsia

    IPC: H04N7/18

    CPC classification number: G06T7/0006 ,  G01N21/9501 ,  G06T2207/10061 ,  G06T2207/30148

    Abstract: A method of forming a device is presented. The method includes providing a substrate containing at least a partially formed device thereon. The device comprises at least one defect site. A pixilated image of the defect site is acquired, and each pixel comprises a grey level value (GLV). Surrounding noises of the defect site is eliminated. A point of the image is identified as the center of the defect. A plurality of iterations to exclude outer edge pixels surrounding the center of the defect image is performed. The defect is categorized as a killer or non-killer defect.

    Abstract translation: 提出了一种形成装置的方法。 该方法包括提供在其上至少包含部分形成的器件的衬底。 该装置包括至少一个缺陷部位。 获取缺陷部位的像素化图像，并且每个像素包括灰度值（GLV）。 消除了缺陷部位的周围噪声。 图像的一个点被识别为缺陷的中心。 执行多个迭代以排除围绕缺陷图像的中心的外边缘像素。 该缺陷被归类为杀伤或非杀伤性缺陷。

    Accurate wafer patterning method for mass production
    6.
    发明授权
    Accurate wafer patterning method for mass production 失效
    准确的晶片图案化方法进行批量生产

    公开(公告)号：US06586143B1

    公开(公告)日：2003-07-01

    申请号：US09619359

    申请日：2000-07-19

    Applicant: Juan Boon Tan ,  Tak Yan Tse ,  Sajan Marokkey Raphael ,  Fang Hong Gn

    Inventor： Juan Boon Tan ,  Tak Yan Tse ,  Sajan Marokkey Raphael ,  Fang Hong Gn

    IPC: G03F900

    CPC classification number: H01L23/544 ,  G03F7/70425 ,  G03F7/70633 ,  G03F9/7084 ,  H01L22/26 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method for checking the position of alignment marks after a chemical mechanical polishing (CMP) process and automatically compensating for alignment of a wafer stepper based on the position checking is described. A wafer is provided having an alignment mark thereon for the purpose of aligning a reticle in the wafer stepper. The wafer is polished by CMP. Thereafter, alignment mark positioning is checked for deviation from a normal vectorial position of the alignment mark whereby information about the deviation is fed back to the wafer stepper and wherein the wafer stepper automatically compensates for correctable alignment error based on the deviation information.

    Abstract translation: 描述了一种用于在化学机械抛光（CMP）处理之后检查对准标记的位置并基于位置检查自动补偿晶片步进器的对准的方法。 提供其上具有其上的对准标记的晶片，用于对准晶片步进机中的掩模版。 通过CMP抛光晶片。 此后，检查对准标记定位与对准标记的正常矢量位置的偏离，从而将关于偏差的信息反馈到晶片步进器，并且其中晶片步进器基于偏差信息自动补偿可校正的对准误差。

    Semiconductor contact metallization
    7.
    发明授权
    Semiconductor contact metallization 失效
    半导体接触金属化

    公开(公告)号：US5677238A

    公开(公告)日：1997-10-14

    申请号：US638667

    申请日：1996-04-29

    Applicant: Fang Hong Gn ,  Sekar Ramamoorthy ,  Lap Chan ,  Che-Chia Wei

    Inventor： Fang Hong Gn ,  Sekar Ramamoorthy ,  Lap Chan ,  Che-Chia Wei

    IPC: H01L21/285 ,  H01L21/768 ,  H01L21/283

    CPC classification number: H01L21/76846 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76843

    Abstract: A method for fabricating an improved connection between active device regions in silicon, to an overlying metallization level, has been developed. The method produces contacts with superior and improved barrier integrity, which permits silicon device exposure to extended thermal process times and/or higher temperature processes without metal penetration into the silicon contact junction regions. The critical element is the addition of a conformal CVD tungsten layer in the multilayer barrier structure.

    Abstract translation: 已经开发了用于制造硅中的有源器件区域与覆盖金属化水平之间的改进连接的方法。 该方法产生具有优异和改善的屏障完整性的触点，其允许硅器件暴露于延长的热处理时间和/或较高温度过程，而不会金属渗入硅接触接合区域。 关键元素是在多层阻挡结构中添加共形CVD钨层。

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