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    Semiconductor wafer testing structure
    2.
    发明授权
    Semiconductor wafer testing structure 失效
    半导体晶圆测试结构

    公开(公告)号：US06273400B1

    公开(公告)日：2001-08-14

    申请号：US09037675

    申请日：1998-03-10

    Applicant: Daniel M. Kuchta

    Inventor： Daniel M. Kuchta

    IPC: H01L2358

    CPC classification number: H01S5/0261 ,  G01R31/2822 ,  G01R31/2831 ,  G01R31/2884 ,  G01R31/316 ,  H01S5/0042 ,  H01S5/0201 ,  H01S5/0422 ,  H01S5/0428 ,  H01S5/183

    Abstract: The present invention is a structure and method to reduce the inductance of the AC test signal path used for testing an electrical device contained within a semiconductor wafer. This extends the frequency range of testing. It enables testing the devices performance characteristics at higher frequencies than otherwise useable. It is particularly directed for testing on-wafer VCSELs. The method provides to the electrical device the characteristics of a microwave bias-tee device. An on wafer capacitor is designed into the environment of the electrical device enabling the formation and use of the three ports of a bias-tee. Preferably, the bias-tee is formed in a manner not requiring the addition of processing steps to the wafer manufacturing process. The method further provides a way to increase the capacitance of the on-wafer capacitor.

    Abstract translation: 本发明是减少用于测试包含在半导体晶片内的电气装置的AC测试信号路径的电感的结构和方法。 这扩大了测试的频率范围。 它能够在比其他可用的频率更高的频率下测试设备性能特性。 它特别针对测试晶圆上的VCSEL。 该方法向电气设备提供了微波偏置三通装置的特性。 晶片电容器设计在电气设备的环境中，能够形成和使用偏置三通的三个端口。 优选地，偏置三通以不需要向晶片制造过程添加处理步骤的方式形成。 该方法还提供了增加晶圆上电容器的电容的方法。

    Semiconductor wafer testing method and apparatus
    3.
    发明授权
    Semiconductor wafer testing method and apparatus 失效
    半导体晶圆测试方法和装置

    公开(公告)号：US5891746A

    公开(公告)日：1999-04-06

    申请号：US37466

    申请日：1998-03-10

    Applicant: Daniel M. Kuchta

    Inventor： Daniel M. Kuchta

    IPC: G01R31/28 ,  G01R31/316 ,  H01S5/00 ,  H01S5/02 ,  H01S5/042 ,  H01S5/183 ,  H01S3/103

    CPC classification number: H01S5/0042 ,  G01R31/2822 ,  G01R31/2831 ,  G01R31/2884 ,  G01R31/316 ,  H01S5/0201 ,  H01S5/0261 ,  H01S5/0422 ,  H01S5/183

    Abstract: The present invention is a structure and method to reduce the inductance of the AC test signal path used for testing an electrical device contained within a semiconductor wafer. This extends the frequency range of testing. It enables testing the device's performance characteristics at higher frequencies than otherwise useable. It is particularly directed for testing on-wafer VCSELs. The method provides to the electrical device the characteristics of a microwave bias-tee device. An on wafer capacitor is designed into the environment of the electrical device enabling the formation and use of the three ports of a bias-tee. Preferably, the bias-tee is formed in a manner not requiring the addition of processing steps to the wafer manufacturing process. The method further provides a way to increase the capacitance of the on-wafer capacitor.

    Abstract translation: 本发明是减少用于测试包含在半导体晶片内的电气装置的AC测试信号路径的电感的结构和方法。 这扩大了测试的频率范围。 它能够以比其他可用的更高的频率测试设备的性能特征。 它特别针对测试晶圆上的VCSEL。 该方法向电气设备提供了微波偏置三通装置的特性。 晶片电容器设计在电气设备的环境中，能够形成和使用偏置三通的三个端口。 优选地，偏置三通以不需要向晶片制造过程添加处理步骤的方式形成。 该方法还提供了增加晶圆上电容器的电容的方法。

    NODE INTERCONNECT ARCHITECTURE TO IMPLEMENT HIGH-PERFORMANCE SUPERCOMPUTER
    5.
    发明申请
    NODE INTERCONNECT ARCHITECTURE TO IMPLEMENT HIGH-PERFORMANCE SUPERCOMPUTER 有权
    节点互连结构实现高性能超级计算机

    公开(公告)号：US20130151812A1

    公开(公告)日：2013-06-13

    申请号：US13313145

    申请日：2011-12-07

    Applicant: Evan G. Colgan ,  Monty M. Denneau ,  Daniel M. Kuchta

    Inventor： Evan G. Colgan ,  Monty M. Denneau ,  Daniel M. Kuchta

    IPC: G06F15/76 ,  G06F9/02

    CPC classification number: H04B10/40 ,  G06F15/161 ,  G06F15/163 ,  G06F15/173 ,  G06F15/17337 ,  H04B10/2503 ,  H04L5/14

    Abstract: Node Interconnect architectures to implement a high performance supercomputer are provided. For example, a node interconnect architecture for connecting a multitude of nodes (or processors) of a supercomputer is implemented using an all-to-all electrical and optical connection network which provides two independent communication paths between any two processors of the supercomputer, wherein a communication path includes at most two electrical links and one optical link.

    Abstract translation: 提供节点互连架构来实现高性能超级计算机。 例如，用于连接超级计算机的多个节点（或处理器）的节点互连体系架构是使用提供超级计算机的任何两个处理器之间的两个独立通信路径的全对电连接网络来实现的，其中a 通信路径最多包括两个电连接和一个光链路。

    Methods and apparatus for optical modulation amplitude measurement
    6.
    发明授权
    Methods and apparatus for optical modulation amplitude measurement 失效
    用于光调制幅度测量的方法和装置

    公开(公告)号：US07885540B2

    公开(公告)日：2011-02-08

    申请号：US12114374

    申请日：2008-05-02

    Applicant: Casimer DeCusatis ,  Daniel M. Kuchta ,  Jeremy Daniel Schaub

    Inventor： Casimer DeCusatis ,  Daniel M. Kuchta ,  Jeremy Daniel Schaub

    IPC: H04B10/08 ,  G01M11/00

    CPC classification number: G01M11/333 ,  G01M11/30

    Abstract: Techniques for measuring optical modulation amplitude (OMA) are disclosed. For example, a technique for measuring an OMA value associated with an input signal includes the following steps/operations. The input signal is applied to a photodetector, wherein the photodetector is calibrated to have a given responsivity value R, and further wherein the photodetector generates an output signal in response to the input signal. The output signal from the photodetector is applied to a radio frequency (RF) power meter, wherein the RF power meter measures the root mean squared (RMS) power value of the output signal received from the photodetector. The OMA value associated with the input signal is determined in response to the root mean squared (RMS) power value measured by the RF power meter. The OMA value may be determined as a function of a factor F derived from a relationship between an amplitude of a data signal and the RMS value of the data signal.

    Abstract translation: 公开了用于测量光调制幅度（OMA）的技术。 例如，用于测量与输入信号相关联的OMA值的技术包括以下步骤/操作。 输入信号被施加到光电检测器，其中光电检测器被校准为具有给定的响应值R，并且其中光电检测器响应于输入信号产生输出信号。 来自光电检测器的输出信号被施加到射频（RF）功率计，其中RF功率计测量从光电检测器接收的输出信号的均方根（RMS）功率值。 响应于由RF功率计测得的均方根（RMS）功率值，确定与输入信号相关的OMA值。 可以根据数据信号的幅度与数据信号的RMS值之间的关系导出的因子F的函数来确定OMA值。

    Method and apparatus for a scalable parallel computer based on optical fiber broadcast
    7.
    发明授权
    Method and apparatus for a scalable parallel computer based on optical fiber broadcast 有权
    基于光纤广播的可扩展并行计算机的方法和装置

    公开(公告)号：US07062121B2

    公开(公告)日：2006-06-13

    申请号：US10295255

    申请日：2002-11-15

    Applicant: Blake G. Fitch ,  Robert S. Germain ,  Glen W. Johnson ,  Daniel M. Kuchta ,  Jeannine M. Trewhella

    Inventor： Blake G. Fitch ,  Robert S. Germain ,  Glen W. Johnson ,  Daniel M. Kuchta ,  Jeannine M. Trewhella

    IPC: G02B6/28

    CPC classification number: G06E1/00

    Abstract: An information processing system, includes several processors, each having at least one optical fiber input and at least one optical fiber output; a controller having an optical fiber input and at least one fiber output; fibers, bundled for transmitting information; and a fiber bundle redriver, coupled to the controller, having an input channel and an output channel, for simultaneously redriving an optical signal received from any selected one of the plurality of input fibers onto substantially all of the plurality of output fibers. The fiber output of each of the plurality of processors and the at least one fiber output of the controller are respectively is coupled to the input channel of the fiber bundle redriver, and the at least one fiber input of each of said plurality of processors and the fiber input of the controller are respectively coupled to the output channel of the fiber bundle redriver.

    Abstract translation: 信息处理系统包括几个处理器，每个处理器具有至少一个光纤输入和至少一个光纤输出; 具有光纤输入和至少一个光纤输出的控制器; 捆绑的光纤，用于传输信息; 以及耦合到所述控制器的具有输入通道和输出通道的光纤束驱动器，用于同时将从所述多个输入光纤中的任何选定的输入光纤接收的光信号重新分配到基本上所有多个输出光纤上。 多个处理器中的每一个的光纤输出和控制器的至少一个光纤输出分别耦合到光纤束转接器的输入通道，并且所述多个处理器中的每一个的至少一个光纤输入和 控制器的光纤输入分别耦合到光纤束转接器的输出通道。

    Circuit for interfacing a first type of logic circuit with a second type of logic circuit
    8.
    发明授权
    Circuit for interfacing a first type of logic circuit with a second type of logic circuit 失效
    用于将第一类逻辑电路与第二类逻辑电路接口的电路

    公开(公告)号：US6111430A

    公开(公告)日：2000-08-29

    申请号：US104602

    申请日：1998-06-24

    Applicant: Daniel M. Kuchta ,  Jungwook Yang

    Inventor： Daniel M. Kuchta ,  Jungwook Yang

    IPC: H03K19/0185 ,  H03K19/0175 ,  H03K19/094 ,  H03K19/20

    CPC classification number: H03K19/018535

    Abstract: A circuit for interfacing CMOS logic devices, having an output level range associated therewith, with MESFET logic devices, having an input level range associated therewith, comprises a depletion mode MESFET device, coupled between at least one CMOS device and at least one other MESFET device, the depletion mode MESFET device limiting a current through a gate-source junction thereof such that the output level range of the at least one CMOS device is altered to be compatible with the input level range of the at least one other MESFET device. Another circuit for interfacing CMOS logic devices, having an output level range associated therewith, with MESFET logic devices, having an input level range associated therewith, comprises: a source follower MESFET device coupled to an output terminal of at least one CMOS device; a first depletion mode MESFET device, coupled to the source follower MESFET device, the first depletion mode MESFET device limiting a current through a gate-source juction thereof such that the output level range of the at least one CMOS device is altered to be compatible with the input level range of at least one other MESFET device; and a second depletion mode MESFET device, coupled to the first depletion mode MESFET device, for providing a discharge path; wherein an input terminal of the at least one other MESFET device is coupled between the first and second depletion mode MESFET devices.

    Abstract translation: 用于与具有与其相关联的输入电平范围的MESFET逻辑器件具有与其相关联的具有输出电平范围的CMOS逻辑器件的电路包括耗尽型MESFET器件，耦合在至少一个CMOS器件与至少一个其它MESFET器件 耗尽型MESFET器件限制通过栅极 - 源极结的电流，使得至少一个CMOS器件的输出电平范围被改变为与至少一个其它MESFET器件的输入电平范围兼容。 用于与具有与其相关联的输入电平范围的具有MESFET逻辑器件的具有与其相关联的输出电平范围的CMOS逻辑器件的接口的另一电路包括：耦合到至少一个CMOS器件的输出端的源极跟随器MESFET器件; 耦合到源极跟随器MESFET器件的第一耗尽型MESFET器件，第一耗尽型MESFET器件限制通过栅极源极漏极的电流，使得至少一个CMOS器件的输出电平范围被改变为与 至少一个其它MESFET器件的输入电平范围; 以及耦合到所述第一耗尽型MESFET器件的用于提供放电路径的第二耗尽型MESFET器件; 其中所述至少一个其它MESFET器件的输入端耦合在所述第一和第二耗尽型MESFET器件之间。

    Methods and Apparatus for Optical Modulation Amplitude Measurement
    10.
    发明申请
    Methods and Apparatus for Optical Modulation Amplitude Measurement 失效
    光调制幅度测量方法与装置

    公开(公告)号：US20090245789A1

    公开(公告)日：2009-10-01

    申请号：US12114374

    申请日：2008-05-02

    Applicant: Casimer DeCusatis ,  Daniel M. Kuchta ,  Jeremy Daniel Schaub

    Inventor： Casimer DeCusatis ,  Daniel M. Kuchta ,  Jeremy Daniel Schaub

    IPC: H04B10/08

    CPC classification number: G01M11/333 ,  G01M11/30

    Abstract: Techniques for measuring optical modulation amplitude (OMA) are disclosed. For example, a technique for measuring an OMA value associated with an input signal includes the following steps/operations. The input signal is applied to a photodetector, wherein the photodetector is calibrated to have a given responsivity value R, and further wherein the photodetector generates an output signal in response to the input signal. The output signal from the photodetector is applied to a radio frequency (RF) power meter, wherein the RF power meter measures the root mean squared (RMS) power value of the output signal received from the photodetector. The OMA value associated with the input signal is determined in response to the root mean squared (RMS) power value measured by the RF power meter. The OMA value may be determined as a function of a factor F derived from a relationship between an amplitude of a data signal and the RMS value of the data signal.

    Abstract translation: 公开了用于测量光调制幅度（OMA）的技术。 例如，用于测量与输入信号相关联的OMA值的技术包括以下步骤/操作。 输入信号被施加到光电检测器，其中光电检测器被校准为具有给定的响应度值R，并且其中光电检测器响应于输入信号产生输出信号。 来自光电检测器的输出信号被施加到射频（RF）功率计，其中RF功率计测量从光电检测器接收的输出信号的均方根（RMS）功率值。 响应于由RF功率计测得的均方根（RMS）功率值，确定与输入信号相关的OMA值。 可以根据数据信号的幅度与数据信号的RMS值之间的关系导出的因子F的函数来确定OMA值。

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