公开(公告)号：US08836679B2

公开(公告)日：2014-09-16

申请号：US13567582

申请日：2012-08-06

Applicant: Nan-Ying Lin ,  Yu-Hsin Ting ,  Chung-Lin Fu ,  Wei-Chun Hsu ,  Pei-Hua Chen

Inventor： Nan-Ying Lin ,  Yu-Hsin Ting ,  Chung-Lin Fu ,  Wei-Chun Hsu ,  Pei-Hua Chen

IPC: G09G5/00 ,  G09G3/36

CPC classification number: G09G3/3611 ,  G09G3/3685 ,  G09G2310/0297

Abstract: In one aspect, an LCD includes a display panel with a pixel matrix having M scan lines and N data lines, and a multiplexer feed-through compensation circuit, which includes P signal lines for providing P video signals, P multiplexers, and K pairs of control lines providing K pairs of control signals. Each multiplexer is electrically coupled to a corresponding signal line and has K channels. Each channel includes first and second switches parallel-connected between the signal line and a corresponding data line for selectively transmitting the video signal to the corresponding data line. Each pair of control lines is respectively electrically coupled to the first and second switches of a corresponding channel of each multiplexer. Each pair of control signals are configured such that a time turning off one of the first and second switches is earlier than that turning off the other switch.

Abstract translation: 一方面，LCD包括具有M条扫描线和N条数据线的像素矩阵的显示面板和多路复用器馈通补偿电路，其包括用于提供P视频信号的P信号线，P多路复用器和K对 提供K对控制信号的控制线。 每个复用器电耦合到对应的信号线并且具有K个信道。 每个通道包括并联在信号线和相应的数据线之间的第一和第二开关，用于选择性地将视频信号传输到对应的数据线。 每对控制线分别电耦合到每个多路复用器的相应通道的第一和第二开关。 每对控制信号被配置为使得关闭第一和第二开关中的一个的时间早于关闭另一个开关的时间。

公开(公告)号：US20120146962A1

公开(公告)日：2012-06-14

申请号：US13087328

申请日：2011-04-14

Applicant: Wei-Chun Hsu ,  Yu-Hsin Ting ,  Chung-Lin Fu ,  Tsao-Wen Lu ,  Nan-Ying Lin ,  Pei-Hua Chen

Inventor： Wei-Chun Hsu ,  Yu-Hsin Ting ,  Chung-Lin Fu ,  Tsao-Wen Lu ,  Nan-Ying Lin ,  Pei-Hua Chen

IPC: G09G3/36 ,  G09G5/00

CPC classification number: G09G3/3648 ,  G09G3/3677 ,  G09G2320/0214

Abstract: An active liquid crystal display panel includes a pixel array, a gate driving circuit, a data driving circuit, and an analog buffer. The gate driving circuit is used for driving M first scan lines where M is a natural number. The analog buffer is coupled to the gate driving circuit and includes M buffer circuits and a regulator. Each buffer circuit drives a corresponding second scan line according to an output signal of a corresponding first scan line of the M first scan lines, and the regulator is used for maintaining at least one reference voltage supplied to the M buffer circuits.

Abstract translation: 有源液晶显示面板包括像素阵列，栅极驱动电路，数据驱动电路和模拟缓冲器。 栅极驱动电路用于驱动M是自然数的M个第一扫描线。 模拟缓冲器耦合到栅极驱动电路，并包括M个缓冲电路和调节器。 每个缓冲电路根据M个第一扫描线的对应的第一扫描线的输出信号驱动相应的第二扫描线，并且调节器用于保持提供给M个缓冲电路的至少一个参考电压。

公开(公告)号：US20120104402A1

公开(公告)日：2012-05-03

申请号：US12938867

申请日：2010-11-03

Applicant: Pei-Hua Chen ,  Yu-Hsin Ting ,  Chung-Lin Fu ,  Tsao-Wen Lu ,  Nan-Ying Lin ,  Wei-Chun Hsu

Inventor： Pei-Hua Chen ,  Yu-Hsin Ting ,  Chung-Lin Fu ,  Tsao-Wen Lu ,  Nan-Ying Lin ,  Wei-Chun Hsu

IPC: H01L27/12

CPC classification number: H01L27/124

Abstract: In one aspect of the invention, an analog buffer circuit includes a p-channel field effect transistor (PTFT) and an n-channel field effect transistor (NTFT). Each of the PTFT and NTFT has a source region and a drain region defining a channel region therebetween, formed on a substrate such that the drain regions of the PTFT and the NTFT are in substantial contact with each other, a gate layer formed over and insulated from the corresponding channel region, a source electrode insulated from the gate layer and electrically connected to the corresponding source region, and a common drain electrode insulated from the gate layer and the source electrode, and is electrically connected to the drain regions of both the PTFT and the NTFT through a via defined over the depletion region.

Abstract translation: 在本发明的一个方面，模拟缓冲电路包括p沟道场效应晶体管（PTFT）和n沟道场效应晶体管（NTFT）。 PTFT和NTFT中的每一个具有形成在基板上的源极区域和限定其间的沟道区域的漏极区域，使得PTFT和NTFT的漏极区域彼此基本接触;形成在绝缘层上的栅极层 从相应的沟道区域，与栅极层绝缘并电连接到对应的源极区域的源极电极和与栅极层和源极电极绝缘的公共漏电极，并且电连接到两个PTFT的漏极区域 和通过在耗尽区域上定义的通孔的NTFT。

公开(公告)号：US07675234B2

公开(公告)日：2010-03-09

申请号：US11218091

申请日：2005-08-31

Applicant: Chung-Lin Fu ,  Yu-Ting Chien ,  Chun-Chien Chiu

Inventor： Chung-Lin Fu ,  Yu-Ting Chien ,  Chun-Chien Chiu

IPC: H01J17/49

CPC classification number: H01J11/36 ,  H01J9/242 ,  H01J11/12 ,  H01J2211/365 ,  H01J2211/368

Abstract: A plasma display panel and a manufacturing method of barrier ribs thereof are provided. The plasma display panel is divided into a display area and a non-display area located in the periphery of the display area. When discharge space is formed in the display area by barrier ribs, a plurality of honeycomb supporting structures are formed in the non-display area at the same time. The honeycomb supporting structures can increase the yield factor of assembling the substrates, and then the display quality of the plasma display panels can be improved.

Abstract translation: 提供等离子体显示面板及其隔壁的制造方法。 等离子体显示面板分为显示区域和位于显示区域周边的非显示区域。 当通过障壁在显示区域中形成放电空间时，在非显示区域中同时形成多个蜂窝支撑结构。 蜂窝状支撑结构能够提高组装基板的成品率，能够提高等离子体显示面板的显示质量。

公开(公告)号：US08766899B2

公开(公告)日：2014-07-01

申请号：US13087328

申请日：2011-04-14

Applicant: Wei-Chun Hsu ,  Yu-Hsin Ting ,  Chung-Lin Fu ,  Tsao-Wen Lu ,  Nan-Ying Lin ,  Pei-Hua Chen

Inventor： Wei-Chun Hsu ,  Yu-Hsin Ting ,  Chung-Lin Fu ,  Tsao-Wen Lu ,  Nan-Ying Lin ,  Pei-Hua Chen

IPC: G09G3/36 ,  G09G5/00

CPC classification number: G09G3/3648 ,  G09G3/3677 ,  G09G2320/0214

Abstract: An active liquid crystal display panel includes a pixel array, a gate driving circuit, a data driving circuit, and an analog buffer. The gate driving circuit is used for driving M first scan lines where M is a natural number. The analog buffer is coupled to the gate driving circuit and includes M buffer circuits and a regulator. Each buffer circuit drives a corresponding second scan line according to an output signal of a corresponding first scan line of the M first scan lines, and the regulator is used for maintaining at least one reference voltage supplied to the M buffer circuits.

Abstract translation: 有源液晶显示面板包括像素阵列，栅极驱动电路，数据驱动电路和模拟缓冲器。 栅极驱动电路用于驱动M是自然数的M个第一扫描线。 模拟缓冲器耦合到栅极驱动电路，并包括M个缓冲电路和调节器。 每个缓冲电路根据M个第一扫描线的对应的第一扫描线的输出信号驱动相应的第二扫描线，并且调节器用于保持提供给M个缓冲电路的至少一个参考电压。

公开(公告)号：US20130141315A1

公开(公告)日：2013-06-06

申请号：US13661239

申请日：2012-10-26

Applicant: Pei-Hua Chen ,  Yu-Hsin Ting ,  Chung-Lin Fu ,  Tsao-Wen Lu ,  Nan-Ying Lin ,  Wei-Chun Hsu

Inventor： Pei-Hua Chen ,  Yu-Hsin Ting ,  Chung-Lin Fu ,  Tsao-Wen Lu ,  Nan-Ying Lin ,  Wei-Chun Hsu

IPC: G11C19/00 ,  G09G3/20

CPC classification number: G11C19/28 ,  G09G3/3648 ,  G09G3/3677 ,  G09G3/38 ,  G09G2310/0286 ,  G11C19/00 ,  G11C19/184

Abstract: A shift register includes shift register units, in which at least one shift register unit is coupled to a forestage shift register unit and a post-stage shift register unit, where the at least one shift register unit includes a signal input circuit, a signal output circuit, a pull down circuit and a switching circuit. The signal input circuit electrically coupled to the forestage shift register unit can receive a logic signal from the forestage shift register. The signal output circuit is electrically coupled to the signal input circuit via a control signal terminal and is electrically coupled to the post-stage shift register unit. The signal output to circuit can receive a first clock signal. The pull down circuit is electrically coupled to or electrically isolated from the control signal terminal through the switching circuit.

Abstract translation: 移位寄存器包括移位寄存器单元，其中至少一个移位寄存器单元耦合到林格移位寄存器单元和后级移位寄存器单元，其中至少一个移位寄存器单元包括信号输入电路，信号输出 电路，下拉电路和开关电路。 电连接到林间移位寄存器单元的信号输入电路可以从林格移位寄存器接收逻辑信号。 信号输出电路经由控制信号端子电耦合到信号输入电路，并且电耦合到后级移位寄存器单元。 输出到电路的信号可以接收第一个时钟信号。 下拉电路通过开关电路与控制信号端子电耦合或电隔离。

公开(公告)号：US20130127697A1

公开(公告)日：2013-05-23

申请号：US13458026

申请日：2012-04-27

Applicant: Nan-Ying LIN ,  Yu-Hsin TING ,  Chung-Lung LI ,  Chung-Lin FU ,  Wei-Chun HSU ,  Pei-Hua CHEN

Inventor： Nan-Ying LIN ,  Yu-Hsin TING ,  Chung-Lung LI ,  Chung-Lin FU ,  Wei-Chun HSU ,  Pei-Hua CHEN

IPC: G09G3/36 ,  H03K17/56

CPC classification number: G09G3/3611 ,  G09G2310/0297

Abstract: A multiplexer circuit includes multiple groups of switches and multiple groups of control lines. Each control line in each one of the groups of control lines is coupled to a control end of at least one switch in corresponding one of the groups of switches, and each group of control lines is configured for synchronously transmitting an identical group of control signals. A display panel and method for transmitting signals in a display panel is also disclosed herein.

Abstract translation: 多路复用器电路包括多组开关和多组控制线。 每组控制线路中的每一组中的每个控制线耦合到开关组中的相应一组中的至少一个开关的控制端，并且每组控制线被配置为同步地发送相同的一组控制信号。 本文还公开了一种用于在显示面板中传输信号的显示面板和方法。

公开(公告)号：US20100112888A1

公开(公告)日：2010-05-06

申请号：US12686600

申请日：2010-01-13

Applicant: Chung-Lin Fu ,  Yu-Ting Chien ,  Chun-Chieh Chiu

Inventor： Chung-Lin Fu ,  Yu-Ting Chien ,  Chun-Chieh Chiu

IPC: H01J9/00

CPC classification number: H01J11/36 ,  H01J9/242 ,  H01J11/12 ,  H01J2211/365 ,  H01J2211/368

Abstract: A manufacturing method of barrier ribs of a plasma display panel is provided. First, a substrate, divided into a display area and a non-display area located in the periphery of the display area, is provided. Next, when a patterned barrier material layer forms on the substrate, the layer further constitutes discharging spaces in the display area and a plurality of honeycomb supporting structures in the non-display area.

Abstract translation: 提供等离子体显示面板的隔壁的制造方法。 首先，提供分割为显示区域和位于显示区域周边的非显示区域的基板。 接下来，当在基板上形成图案化阻挡材料层时，该层进一步构成显示区域中的放电空间和非显示区域中的多个蜂窝支撑结构。

公开(公告)号：US20090278783A1

公开(公告)日：2009-11-12

申请号：US12348490

申请日：2009-01-05

Applicant: Yu-hsin Ting ,  Chung-lin Fu ,  Chun-yen Liu

Inventor： Yu-hsin Ting ,  Chung-lin Fu ,  Chun-yen Liu

IPC: G09G3/36

CPC classification number: G09G3/3688 ,  G09G2310/0281

Abstract: A display device includes a substrate, a display area, an ASIC disposed by a first edge of the display area for generating a number of P data voltage signals, a first shift register having a plurality of first shift register units disposed by a second edge of the display area, a second shift register having a plurality of second shift register units disposed by a third edge of the display area, a plurality of first switch unit and a plurality of second units. The first switch units sequentially outputs the first through the P 2  th data voltage signals to the display area in response to first control signal from the first shift register units, simultaneously, the second switch units sequentially outputs the ( P 2 + 1 )  th through the Pth data voltage signals to the display area in response to second control signal from the second shift register units.

Abstract translation: 显示装置包括基板，显示区域，由显示区域的第一边缘设置的ASIC，用于产生多个P数据电压信号;第一移位寄存器，具有多个第一移位寄存器单元， 显示区域，具有由显示区域的第三边缘布置的多个第二移位寄存器单元的第二移位寄存器，多个第一开关单元和多个第二单元。 第一开关单元响应于来自第一移位寄存器单元的第一控制信号，顺序地将第一至第二数据电压信号输出到显示区域，同时第二开关单元依次输出（P 2 + 1） 响应于来自第二移位寄存器单元的第二控制信号，通过Pth数据电压信号传送到显示区域。

公开(公告)号：US20110292005A1

公开(公告)日：2011-12-01

申请号：US12940765

申请日：2010-11-05

Applicant: Chee-Wai LAU ,  Yu-Hsin Ting ,  Chung-Lin Fu ,  Wei-Chun Hsu ,  Nan-Ying Lin ,  Fu-Yuan Liou

Inventor： Chee-Wai LAU ,  Yu-Hsin Ting ,  Chung-Lin Fu ,  Wei-Chun Hsu ,  Nan-Ying Lin ,  Fu-Yuan Liou

IPC: G09G5/00

CPC classification number: G09G3/3677 ,  G09G3/3688 ,  G09G2320/0257 ,  G09G2330/027

Abstract: A display apparatus includes a plurality of scan lines, a plurality of data lines, a plurality of pixel transistors, a plurality of pixel electrodes, a gate driver, a source driver and a discharge circuit. The data lines are intersected with the scan lines. Each of the pixel transistors is electrically coupled to a corresponding scan line and a corresponding data line, and each of the pixel electrodes is electrically coupled to a corresponding pixel transistor. The gate driver is electrically coupled to the scan lines, and the source driver is electrically coupled to the data lines. The discharge circuit is electrically coupled to the gate driver and the data lines. The discharge circuit starts when the display apparatus is turned off, to control the gate drive for turning on the pixel transistors simultaneously, and make the pixel electrodes be electrically communicated with a reference voltage.

Abstract translation: 显示装置包括多条扫描线，多条数据线，多个像素晶体管，多个像素电极，栅极驱动器，源极驱动器和放电电路。 数据线与扫描线相交。 每个像素晶体管电耦合到对应的扫描线和对应的数据线，并且每个像素电极电耦合到相应的像素晶体管。 栅极驱动器电耦合到扫描线，并且源极驱动器电耦合到数据线。 放电电路电耦合到栅极驱动器和数据线。 当显示装置关闭时，放电电路开始，同时控制栅极驱动以同时开启像素晶体，并使像素电极与基准电压电连通。