-
公开(公告)号：US07079386B1
公开(公告)日：2006-07-18
申请号：US10390243
申请日：2003-03-17
Applicant: Daniel A. Jochym , Christian E. Shenberger , Keith D. Mease , Joseph J. Scorsone
Inventor： Daniel A. Jochym , Christian E. Shenberger , Keith D. Mease , Joseph J. Scorsone
IPC: G06F1/20
CPC classification number: G06F1/183
Abstract: A computer system is provided with a rack defining an interior. A computer chassis is mounted at least partially within the interior of the rack, wherein the computer chassis defines an interior. An interconnect assembly is mounted at least partially within the interior of the rack, wherein the interconnect assembly has an interconnect connector. A processor assembly is mounted at least partially within the interior of the computer chassis, and the processor assembly has a processor board and a processor connector mounted to the processor board and connected to the interconnect connector of the interconnect assembly. The processor assembly also has at least eight addressable processor segments mounted to the processor board.
Abstract translation: 计算机系统设置有限定内部的机架。 计算机机箱至少部分地安装在机架的内部，其中计算机机箱限定内部。 互连组件至少部分地安装在机架的内部，其中互连组件具有互连连接器。 处理器组件至少部分地安装在计算机机箱的内部，并且处理器组件具有安装到处理器板并连接到互连组件的互连连接器的处理器板和处理器连接器。 处理器组件还具有安装到处理器板的至少八个可寻址处理器段。
-
公开(公告)号：US06842344B1
公开(公告)日：2005-01-11
申请号：US10390383
申请日：2003-03-17
Applicant: Robert Fix , Daniel A. Jochym , Christian E. Shenberger
Inventor： Robert Fix , Daniel A. Jochym , Christian E. Shenberger
CPC classification number: H05K1/0216 , H05K1/0298 , H05K2201/09336
Abstract: A printed circuit board having a dielectric layer is disclosed. At least one signal trace is disposed adjacent a first surface of the dielectric layer in a first signal area. A reference plane is disposed adjacent a second surface of the dielectric layer in a first reference area positioned opposite the first signal area. The reference plane is configured to carry a reference potential for signals on the signal trace. At least one other signal trace is disposed adjacent the second surface of the dielectric layer in a second signal area and coupled to the signal trace in said first signal area. A second reference plane is disposed adjacent the first surface of the first dielectric layer in a second reference area positioned opposite the second signal area. The second reference plane is configured to carry the reference potential for signals on the other signal trace.
Abstract translation: 公开了一种具有电介质层的印刷电路板。 在第一信号区域中，邻近电介质层的第一表面设置至少一个信号迹线。 在与第一信号区域相对定位的第一参考区域中，在电介质层的第二表面附近设置参考平面。 参考平面被配置为对信号迹线上的信号携带参考电位。 至少一个其它信号迹线被布置在第二信号区域中与电介质层的第二表面相邻并且耦合到所述第一信号区域中的信号迹线。 在与第二信号区域相对定位的第二参考区域中，第二参考平面设置在第一介电层的第一表面附近。 第二参考平面被配置为对另一信号迹线上的信号携带参考电位。
-
公开(公告)号：US07040013B1
公开(公告)日：2006-05-09
申请号：US10390368
申请日：2003-03-17
Applicant: Daniel A. Jochym , Christian E. Shenberger , Robert Fix
Inventor： Daniel A. Jochym , Christian E. Shenberger , Robert Fix
IPC: H05K3/02
CPC classification number: H05K1/0216 , H05K1/112 , H05K1/115 , H05K2201/09227 , H05K2201/09263 , H05K2201/09609 , H05K2201/10734 , Y10T29/49117 , Y10T29/49155 , Y10T29/49156 , Y10T29/49162 , Y10T29/49718
Abstract: A method, system, and product for routing nets along a printed circuit board through an obstacle field and a circuit board having traces produced in accordance with the routed nets is disclosed. The nets are routed by identifying a general path for each of a pair of nets between adjacent rows of obstacles within an obstacle field, selectively lengthening at least one of the nets by shifting at least one portion of the net toward a position between adjacent pads in one of the rows, thereby increasing the length of the net, and selectively increasing the mean spacing between the pair of nets by shifting at least one portion of at least one net of the pair away from the other net of the pair toward a position between adjacent pads in one of the rows, thereby reducing cross-talk between the nets.
Abstract translation: 公开了一种用于通过障碍物场沿着印刷电路板路由网络的方法，系统和产品，以及具有根据所传送的网络产生的迹线的电路板。 通过识别障碍物区域内的相邻障碍物排之间的一对网络中的每一个网络的通用路径来路由网络，通过将网络的至少一部分移向相邻焊盘之间的位置来选择性地延长网络中的至少一个网络 从而增加网的长度，并且通过将对中的至少一个网的至少一个部分从另一个网络的至少一个部分移动到另一个网络之间的位置来选择性地增加该对网之间的平均间隔 在一行中的相邻焊盘，从而减少网之间的串扰。
-
公开(公告)号：US06818838B1
公开(公告)日：2004-11-16
申请号：US10390869
申请日：2003-03-17
Applicant: Daniel A. Jochym , Christian E. Shenberger , Joseph N. Closs
Inventor： Daniel A. Jochym , Christian E. Shenberger , Joseph N. Closs
IPC: H05K1204
CPC classification number: H05K1/181 , H05K1/0298 , H05K2201/09227 , H05K2201/10522 , Y02P70/611
Abstract: An apparatus and method for positioning components on a circuit board and routing traces therebetween is disclosed. The circuit board has two pairs of electrical component-receiving footprint and a plurality of traces interconnecting the footprints. The two pairs of electrical component-receiving footprints are spaced from one another in a first direction, wherein the footprints in each of the pairs are substantially aligned in a second direction substantially perpendicular to the first direction, and wherein at least one of the footprints in one of the pairs is offset from at least one of the footprints in the other of the pairs in both the first and second directions. The plurality of traces interconnect each of the footprints includes at least one trace connecting the offset footprints. The trace has a first portion extending from one of the offset footprints toward the other one of the offset footprints in substantially the first direction, a second portion extending from the other one of the offset footprints toward the one of said offset footprints in substantially the first direction, and a third portion extending between the first portion and the second portion in substantially the second direction.
Abstract translation: 公开了一种用于将部件定位在电路板上并在其间布线迹线的装置和方法。 电路板具有两对电气元件接收覆盖区和互连占地面积的多条迹线。 两对电气部件接收脚印在第一方向上彼此间隔开，其中每对中的脚印基本上在基本上垂直于第一方向的第二方向上对齐，并且其中至少一个脚印在 成对中的一个与第一和第二方向上的另一对中的至少一个印迹偏移。 互连每个覆盖区的多个迹线包括连接偏移覆盖区的至少一个迹线。 迹线具有从基本上第一方向上的偏移覆盖区中的一个延伸到另一个偏移覆盖区的第一部分，第二部分从多个偏移覆盖区中的另一个延伸到基本上第一个 方向，以及在大致第二方向上在第一部分和第二部分之间延伸的第三部分。
-
-
-
Search Results
4
records
(took 0.011 seconds)
