公开(公告)号：US08488657B2

公开(公告)日：2013-07-16

申请号：US12794152

申请日：2010-06-04

Applicant: Miaochen Wu ,  Brian L. Dellacroce

Inventor： Miaochen Wu ,  Brian L. Dellacroce

IPC: H04L5/16

CPC classification number: H03L7/0807 ,  H03L7/0812 ,  H03L7/0814 ,  H04L7/0025 ,  H04L7/0337

Abstract: A system comprises a first circuit includes a data transmitter circuit that transmits digital data based on a first clock signal. A sync generator outputs a sync signal based on the first clock signal. A digital to analog converter circuit includes a data receiver circuit that latches the digital data based on a second clock signal. A digital to analog converter core receives an output of the data receiver circuit. A delay locked loop circuit determines a delay based on the second clock signal and the sync signal and outputs the first clock signal to the first circuit based on the second clock signal and the delay.

Abstract translation: 系统包括第一电路，其包括基于第一时钟信号发送数字数据的数据发送器电路。 同步发生器基于第一时钟信号输出同步信号。 数模转换器电路包括基于第二时钟信号锁存数字数据的数据接收器电路。 数模转换器内核接收数据接收电路的输出。 延迟锁定环电路基于第二时钟信号和同步信号确定延迟，并且基于第二时钟信号和延迟将第一时钟信号输出到第一电路。

公开(公告)号：US20110298508A1

公开(公告)日：2011-12-08

申请号：US12794152

申请日：2010-06-04

Applicant: Miaochen Wu ,  Brian L. Dellacroce

Inventor： Miaochen Wu ,  Brian L. Dellacroce

IPC: H03L7/06

CPC classification number: H03L7/0807 ,  H03L7/0812 ,  H03L7/0814 ,  H04L7/0025 ,  H04L7/0337

Abstract: A system comprises a first circuit includes a data transmitter circuit that transmits digital data based on a first clock signal. A sync generator outputs a sync signal based on the first clock signal. A digital to analog converter circuit includes a data receiver circuit that latches the digital data based on a second clock signal. A digital to analog converter core receives an output of the data receiver circuit. A delay locked loop circuit determines a delay based on the second clock signal and the sync signal and outputs the first clock signal to the first circuit based on the second clock signal and the delay.

Abstract translation: 系统包括第一电路，其包括基于第一时钟信号发送数字数据的数据发送器电路。 同步发生器基于第一时钟信号输出同步信号。 数模转换器电路包括基于第二时钟信号锁存数字数据的数据接收器电路。 数模转换器内核接收数据接收电路的输出。 延迟锁定环电路基于第二时钟信号和同步信号确定延迟，并且基于第二时钟信号和延迟将第一时钟信号输出到第一电路。