公开(公告)号：US07868678B2

公开(公告)日：2011-01-11

申请号：US12167256

申请日：2008-07-03

Applicant: Ban Hok Goh

Inventor： Ban Hok Goh

IPC: H03H11/16

CPC classification number: G01R25/005

Abstract: Embodiments related to configurable differential lines are disclosed herein.

Abstract translation: 本文公开了与可配置差分线相关的实施例。

公开(公告)号：US20100001764A1

公开(公告)日：2010-01-07

申请号：US12167256

申请日：2008-07-03

Applicant: Ban Hok GOH

Inventor： Ban Hok GOH

IPC: G01R25/00

CPC classification number: G01R25/005

Abstract: Embodiments related to configurable differential lines are disclosed herein.

Abstract translation: 本文公开了与可配置差分线相关的实施例。

公开(公告)号：US20080094099A1

公开(公告)日：2008-04-24

申请号：US11543009

申请日：2006-10-04

Applicant: Ban Hok Goh ,  Dieter Draxelmayr

Inventor： Ban Hok Goh ,  Dieter Draxelmayr

IPC: H03K19/003

CPC classification number: H03K5/13 ,  H03K2005/00032 ,  H03K2005/00045 ,  H03K2005/00136 ,  H03L7/0812 ,  H04L25/0272

Abstract: A differential line compensation apparatus is disclosed that has a first terminal to receive a first differential signal supplied by a first trace and a second terminal to receive a second differential signal supplied by a second trace. The apparatus has at least one detector to detect a first condition of a first signal at least related to the first differential signal, and a second condition of a second signal at least related to the second differential signal and to provide an output containing the results of the detections. A comparator is coupled to the at least one detector to receive and process the at least one output and to provide a control output. At least one delay controller receives the control output and applies a phase correction to a selected one of the first signal and the second signal. A corresponding method and system are also disclosed.

公开(公告)号：US06636374B1

公开(公告)日：2003-10-21

申请号：US09556887

申请日：2000-04-19

Applicant: Ban Hok Goh ,  Nan Ling Goh ,  Tze Ming Jimmy Pang ,  Kah Liang Gan ,  LaiKein James Chang

Inventor： Ban Hok Goh ,  Nan Ling Goh ,  Tze Ming Jimmy Pang ,  Kah Liang Gan ,  LaiKein James Chang

IPC: G11B2102

CPC classification number: G11B5/54 ,  G11B19/20 ,  G11B21/12

Abstract: A system for hardware intelligent speed monitoring and auto-retract is disclosed. The system contains a monitoring device that monitors the TACH (Tachometer) output of motor driver. The device provides a trigger to the signal processor and a retract mechanism to retract the actuator when the spindle motor speed is unexpectedly much higher or lower than normal speed. The system DSP (Digital Signal Processor) is unaware of such occurrence.

Abstract translation: 公开了一种用于硬件智能速度监测和自动缩回的系统。 该系统包含监控电机驱动器的TACH（转速表）输出的监控装置。 当主轴电机速度意外地高于或低于正常速度时，该装置向信号处理器提供触发器和一个缩回机构以使致动器缩回。 系统DSP（数字信号处理器）不知道这种情况。

公开(公告)号：US07679450B2

公开(公告)日：2010-03-16

申请号：US12031041

申请日：2008-02-14

Applicant: Ban Hok Goh

Inventor： Ban Hok Goh

IPC: H03F1/14

CPC classification number: H03F3/3069 ,  H03F1/0261 ,  H03F2203/30015 ,  H03F2203/30078 ,  H03F2203/30111

Abstract: This disclosure relates to monitoring signal overshoot of an amplifier generated signal and automatically adjusting a quiescent current of the amplifier as a function of the monitored signal overshoot.

Abstract translation: 本公开涉及监视放大器产生的信号的信号过冲并且根据所监视的信号过冲自动调整放大器的静态电流。

公开(公告)号：US07489167B2

公开(公告)日：2009-02-10

申请号：US11411335

申请日：2006-04-26

Applicant: Ban Hok Goh

Inventor： Ban Hok Goh

IPC: H03L7/00

CPC classification number: G06F1/28 ,  H03K17/223 ,  H03K17/284 ,  Y10T307/50 ,  Y10T307/702

Abstract: A voltage detection and sequencing circuit is provided, preferably on a single semiconductor chip, for applying a plurality of voltages to an electrical system in a predetermined sequence. The circuit includes a plurality of subsystems each adapted to detect one of a plurality of supply voltages at an input terminal and to supply the supply voltage to at least one output terminal in a predetermined sequence as controlled by a sequencing means.

Abstract translation: 提供电压检测和排序电路，优选地在单个半导体芯片上，用于以预定顺序向电气系统施加多个电压。 电路包括多个子系统，每个子系统适于检测输入端子处的多个电源电压中的一个，并且以由排序装置控制的预定顺序将电源电压提供给至少一个输出端子。

公开(公告)号：US20080290960A1

公开(公告)日：2008-11-27

申请号：US11752489

申请日：2007-05-23

Applicant: Ban Hok Goh

Inventor： Ban Hok Goh

IPC: H03H7/38

CPC classification number: H03H7/38 ,  H03H11/28

Abstract: An apparatus includes a bidirectional data line to couple to a device and an impedance to provide an impedance matching between the data line and the device. In some embodiments, when a direction of data flow in the data line is away from the device, the impedance is of a first impedance value, and when the direction of the data flow is toward the device, the impedance is of a second impedance value. In one embodiment, the second impedance value is substantially zero.

Abstract translation: 一种装置包括耦合到装置的双向数据线和阻抗以在数据线和装置之间提供阻抗匹配。 在一些实施例中，当数据线中的数据流的方向远离器件时，阻抗为第一阻抗值，并且当数据流的方向朝向器件时，阻抗为第二阻抗值 。 在一个实施例中，第二阻抗值基本为零。

公开(公告)号：US20080218231A1

公开(公告)日：2008-09-11

申请号：US12111216

申请日：2008-04-29

Applicant: Ban Hok GOH ,  Dieter DRAXELMAYR

Inventor： Ban Hok GOH ,  Dieter DRAXELMAYR

IPC: H03L7/00

CPC classification number: H03K5/13 ,  H03K2005/00032 ,  H03K2005/00045 ,  H03K2005/00136 ,  H03L7/0812 ,  H04L25/0272

Abstract: A differential line compensation apparatus, semiconductor chip and system are disclosed.

Abstract translation: 公开了一种差分线路补偿装置，半导体芯片和系统。

公开(公告)号：US07239172B2

公开(公告)日：2007-07-03

申请号：US11079003

申请日：2005-03-11

Applicant: Ban Hok Goh

Inventor： Ban Hok Goh

IPC: H03K19/003 ,  H03K19/23

CPC classification number: H04L25/0278

Abstract: There is provided apparatus for connecting between a data source or a data receiver and a data line. The apparatus comprises an impedance and an impedance controller arranged to continually adjust the value of the active impedance so as to control the relative impedances of the total source, the total source comprising the data source and the impedance, and the data line or of the total receiver, the total receiver comprising the data receiver and the impedance, and the data line. There is also provided a semiconductor chip, connectable to a data line, the semiconductor chip comprising the apparatus together with a data source or data receiver, as appropriate. There is also provided a method for controlling impedance matching between a data source or data receiver and a data line. The method comprises the steps of providing an impedance connected between the data source or data receiver and the data line; and continually adjusting the value of the impedance so as to control the relative impedances of the total source or total receiver and the data line.

Abstract translation: 提供了用于在数据源或数据接收器与数据线之间连接的装置。 该装置包括阻抗和阻抗控制器，其布置成连续地调节有源阻抗的值，以便控制总源的相对阻抗，包括数据源和阻抗的总源，以及数据线或总数 接收机，包括数据接收机和阻抗的总接收机和数据线。 还提供了可连接到数据线的半导体芯片，包括该装置的半导体芯片以及数据源或数据接收器。 还提供了一种用于控制数据源或数据接收器与数据线之间的阻抗匹配的方法。 该方法包括提供连接在数据源或数据接收器与数据线之间的阻抗的步骤; 并持续调整阻抗值，以便控制总源或总接收器和数据线的相对阻抗。

公开(公告)号：US06519106B1

公开(公告)日：2003-02-11

申请号：US09553073

申请日：2000-04-20

Applicant: Nan Ling Goh ,  Ban Hok Goh ,  Utt Heng Kan ,  Kah Liang Gan

Inventor： Nan Ling Goh ,  Ban Hok Goh ,  Utt Heng Kan ,  Kah Liang Gan

IPC: G11B535

CPC classification number: G11B20/10055 ,  G11B5/02 ,  G11B5/09 ,  G11B20/10009 ,  G11B20/10203 ,  G11B20/10296 ,  G11B2005/0016 ,  G11B2005/0018

Abstract: A method for compensating digital samples of an asymmetric read signal is presented. The method involves reading a digital sample of an asymmetric read signal V(t) (160), generating a compensated sample at least when the digital sample requires compensation (164), and outputting either the digital sample (168) or the compensated sample (166). Also presented is an asymmetry correction block (158) of a read channel (144) of a disc drive (110) that includes an input (200), a level detector (202), a compensator (204), and an output (208). The level detector (202) and the compensator (204) receive the digital sample through the input (200). The level detector (202) determines whether the digital sample requires compensation. The compensator (204) generates a compensated sample at least when the digital sample requires compensation. The output (208) selectively outputs either the digital sample or the compensated sample.

Abstract translation: 提出了一种用于补偿非对称读信号的数字样本的方法。 该方法涉及读取非对称读取信号V（t）（160）的数字样本，至少当数字样本需要补偿时产生补偿样本（164），并输出数字样本（168）或补偿样本 166）。 还提出了包括输入（200），电平检测器（202），补偿器（204）和输出（208）的盘驱动器（110）的读通道（144）的不对称校正块（158） ）。 电平检测器（202）和补偿器（204）通过输入（200）接收数字采样。 电平检测器（202）确定数字样本是否需要补偿。 至少当数字样本需要补偿时，补偿器（204）产生补偿样本。 输出（208）选择性地输出数字样本或补偿样本。