公开(公告)号：US5441768A

公开(公告)日：1995-08-15

申请号：US193310

申请日：1994-02-08

Applicant: Kam S. Law ,  Robert Robertson ,  Michael Kollrack ,  Angela T. Lee ,  Takako Takehara ,  Guofu J. Feng ,  Dan Maydan

Inventor： Kam S. Law ,  Robert Robertson ,  Michael Kollrack ,  Angela T. Lee ,  Takako Takehara ,  Guofu J. Feng ,  Dan Maydan

IPC: H01L21/205 ,  C23C16/24 ,  C23C16/34 ,  H01L21/31 ,  H01L21/318 ,  H01L21/336 ,  H01L29/786 ,  C23C16/22

CPC classification number: H01L29/66765 ,  C23C16/24 ,  C23C16/345

Abstract: An improved method of depositing films of a gate silicon nitride and an amorphous silicon on a thin film transistor substrate at high deposition rates while maintaining superior film quality is provided. The material near the interface between the amorphous silicon and the nitride are deposited at a low deposition rate which produces superior quality films. The region away from the interface are deposited at a high deposition rate which produces lesser, but still good quality films. By using this method, superior quality thin film transistors can be produced at very high efficiency. The method can be carried out by depositing a high quality g-SiN.sub.x at a low deposition rate on top of an average quality gate nitride deposited at a high deposition rate and then depositing an amorphous silicon layer. It also applies in a process where high quality amorphous silicon is first deposited at a low deposition rate on a gate nitride layer to form an interface, and then average quality amorphous silicon is deposited at a high deposition rate to complete the silicon layer. The unique process can be applied whenever an interface exists with an active semiconductor layer of amorphous silicon. The process is applicable to either the back channel etched TFT device or the etch stopped TFT device.

Abstract translation: 提供了一种在保持优异的膜质量的同时以高沉积速率在薄膜晶体管基板上沉积栅极氮化硅和非晶硅的膜的改进方法。 在非晶硅和氮化物之间的界面附近的材料以低沉积速率沉积，其产生优质的膜。 离开界面的区域以高沉积速率沉积，其产生较小但仍然是优质的膜。 通过使用该方法，能够以非常高的效率制造出优质的薄膜晶体管。 该方法可以通过在以高沉积速率沉积的平均质量的氮化镓的顶部上以低沉积速率沉积高质量的g-SiNx，然后沉积非晶硅层来进行。 它也适用于首先在栅极氮化物层上以低沉积速率沉积高品质非晶硅以形成界面的过程，然后以高沉积速率淀积平均质量的非晶硅以完成硅层。 每当与非晶硅的有源半导体层存在界面时，可以应用独特的工艺。 该工艺适用于后沟道蚀刻TFT器件或蚀刻停止的TFT器件。

公开(公告)号：US5380566A

公开(公告)日：1995-01-10

申请号：US080018

申请日：1993-06-21

Applicant: Robert Robertson ,  Marc M. Kollrack ,  Angela T. Lee ,  Kam Law ,  Dan Maydan

Inventor： Robert Robertson ,  Marc M. Kollrack ,  Angela T. Lee ,  Kam Law ,  Dan Maydan

IPC: C23C16/50 ,  C23C16/509 ,  C23C16/56 ,  B05D3/06

CPC classification number: C23C16/56 ,  C23C16/509

Abstract: A method of limiting sticking of a body (substrate) to a susceptor after the body has been coated with a layer in a deposition chamber by plasma chemical vapor deposition includes subjecting the coated body to a plasma of an inactive gas, e.g., hydrogen, nitrogen, argon or ammonia, which does not adversely affect the coating and does not add additional layers to the body. After the coated body is subjected to the plasma of the inactive gas, the body is separated from the susceptor.

Abstract translation: 在通过等离子体化学气相沉积在体积已经在沉积室中涂覆了层之后，将体（衬底）粘附到基座上的方法包括使涂覆体经受惰性气体例如氢气，氮气等离子体 ，氩或氨，其不会对涂层产生不利影响，并且不向身体添加额外的层。 在涂覆体经受惰性气体的等离子体之后，主体与基座分离。

公开(公告)号：US5567476A

公开(公告)日：1996-10-22

申请号：US427772

申请日：1995-04-25

Applicant: Kam S. Law ,  Robert Robertson ,  Michael Kollrack ,  Angela T. Lee ,  Takako Takehara ,  Guofu J. Feng ,  Dan Maydan

Inventor： Kam S. Law ,  Robert Robertson ,  Michael Kollrack ,  Angela T. Lee ,  Takako Takehara ,  Guofu J. Feng ,  Dan Maydan

IPC: H01L21/205 ,  C23C16/24 ,  C23C16/34 ,  H01L21/31 ,  H01L21/318 ,  H01L21/336 ,  H01L29/786 ,  C23C16/00

CPC classification number: H01L29/66765 ,  C23C16/24 ,  C23C16/345

Abstract: A multi-step CVD method for thin film transistor is disclosed. The method can be carried out by depositing a high quality g-SiN.sub.x at a low deposition rate on top of an average quality gate nitride deposited at a high deposition rate and then depositing an amorphous silicon layer. It also applies in a process where high quality amorphous silicon is first deposited at a low deposition rate on a gate nitride layer to form an interface, and then average quality amorphous silicon is deposited at a high deposition rate to complete the silicon layer. The unique process can be applied whenever an interface exists with an active semiconductor layer of amorphous silicon. The process is applicable to either the back channel etched TFT device or the etch stopped TFT device.

Abstract translation: 公开了薄膜晶体管的多步CVD方法。 该方法可以通过在以高沉积速率沉积的平均质量的氮化镓的顶部上以低沉积速率沉积高质量的g-SiNx，然后沉积非晶硅层来进行。 它也适用于首先在栅极氮化物层上以低沉积速率沉积高品质非晶硅以形成界面的过程，然后以高沉积速率淀积平均质量的非晶硅以完成硅层。 每当与非晶硅的有源半导体层存在界面时，可以应用独特的工艺。 该工艺适用于后沟道蚀刻TFT器件或蚀刻停止的TFT器件。