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    Programmable static selection circuit for programmable devices
    2.
    发明授权
    Programmable static selection circuit for programmable devices 失效
    可编程器件的可编程静态选择电路

    公开(公告)号：US4996451A

    公开(公告)日：1991-02-26

    申请号：US411661

    申请日：1989-09-25

    申请人： Antonio Chiriatti ,  Marco Masini

    发明人： Antonio Chiriatti ,  Marco Masini

    IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C16/08

    CPC分类号： G11C16/08

    摘要： The circuit comprises: a pair of programmable cells connected in series, one conducting, the other one open, with one free terminal connected to the ground and the opposite free terminal connected to a supply voltage; a threshold circuit having one input connected to the node between the two programmable cells, a switching threshold lower than the difference between the supply voltage and the threshold voltage of one of the programmable cells, and an output adapted to assume one of two logic levels depending on whether the tension on the input is higher or lower than the threshold; and a first transistor which is connected between the ground and the opposite end of the pair of programmable cells, is normally off and has a gate which can be driven to make it conduct.

    Programmable logic device having a plurality of programmable logic arrays arranged in a mosaic layout together with a plurality of interminglingly arranged interfacing blocks
    3.
    发明授权
    Programmable logic device having a plurality of programmable logic arrays arranged in a mosaic layout together with a plurality of interminglingly arranged interfacing blocks 失效
    具有多个可编程逻辑阵列的可编程逻辑器件与多个混合布置的接口块一起以马赛克布局布置

    公开(公告)号：US4992680A

    公开(公告)日：1991-02-12

    申请号：US456782

    申请日：1989-12-27

    申请人： Mirella Benedetti ,  Antonio Chiriatti ,  Vincenzo Daniele ,  Biagio Giacalone

    发明人： Mirella Benedetti ,  Antonio Chiriatti ,  Vincenzo Daniele ,  Biagio Giacalone

    IPC分类号： H01L21/82 ,  H03K19/173 ,  H03K19/177 ,  H03K23/54

    CPC分类号： H03K19/1735 ,  H03K19/17708 ,  H03K23/542

    摘要： A programmable logic device has an architecture which permits to implement logic functions through loopable multi-levels by utilizing a network of distributed memory arrays organized as a mosaic of arrays of programmable memory cells and multifunctional interfacing blocks. Each of said blocks contains an input selection circuitry capable of receiving input signals coming from bidirectional input/output pins and/or from outputs of said arrays, signal selection means, polarity selection means and path selection means and an output sorting circuitry capable of selecting non-stored or stored type, data containing signals, selecting the polarity and the path of said signals toward enableable output drive buffers of said plurality of bidirectional input/output pins and/or toward the inputs of any one of said arrays, a circuitry capable of producing for each of said signals a first, non-inverted, and a second, inverted, buffered replica signals with which to drive the rows of one or more of said memory arrays for causing the output of signals from those arrays, each array being programmable in order to perform different logic functions for any combination of inputs thereof and the exchange between two different arrays and between an array and the external world taking place essentially through at least one of said multfunctional blocks.

    Field programmable logic and analogic integrated circuit
    5.
    发明授权
    Field programmable logic and analogic integrated circuit 失效
    现场可编程逻辑和模拟集成电路

    公开(公告)号：US4952934A

    公开(公告)日：1990-08-28

    申请号：US465703

    申请日：1990-01-16

    申请人： Antonio Chiriatti

    发明人： Antonio Chiriatti

    IPC分类号： G05B15/02 ,  G05B19/045 ,  G06J1/00

    CPC分类号： G05B19/045 ,  G05B15/02 ,  G06J1/00 ,  Y10T307/826

    摘要： A programmable logic and analogic integrated device comprises a programmable logic section capable of constituting by programming a state machine which beside producing outpout logic signals in function of input logic signals may drive a digital-analog converter (DAC), the analog signal generated by which is managed as well as other analog signals which may be respectively fed to a number of analog input pins of the integrated device by the said programmable state machine by means of a plurality of integrated analog switches which also permit the output of the analog signal generated by the DAC through a buffered analog output pin of the device. An integrated comparator (zero-crossing detector) provides a comparison between two distinct external analog signals or between an external analog signal and the analog signal generated by the DAC for producing an output logic signal which may be fed to an input of the state machine for implementing a certain interaction function.The device is useful for a wide range of applications in lieu of a microprocessor based system.

    摘要翻译： 可编程逻辑和模拟集成装置包括能够通过编程状态机构成的可编程逻辑部分，其旁边产生输入逻辑信号功能的输出逻辑信号可以驱动数模转换器（DAC），由其产生的模拟信号 管理以及可以通过多个集成模拟开关分别馈送到所述可编程状态机的集成设备的多个模拟输入引脚的其他模拟信号，所述多个集成模拟开关还允许输出由 DAC通过缓冲模拟输出引脚的器件。 集成比较器（过零检测器）提供两个不同的外部模拟信号之间或外部模拟信号与DAC产生的模拟信号之间的比较，用于产生输出逻辑信号，该输出逻辑信号可被馈送到状态机的输入端 实现一定的互动功能。 该设备对于广泛的应用代替基于微处理器的系统是有用的。