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公开(公告)号：US20240348768A1
公开(公告)日：2024-10-17
申请号：US18681781
申请日：2021-08-31
发明人： Gajinder PANESAR , Marcin HLOND
CPC分类号： H04N17/002 , G01J1/44 , G01J2001/444
摘要： A method of monitoring messages from a sensor using an integrated circuit is provided, wherein the messages include data measured by that sensor. The method includes reading a first message from interconnect circuitry of the integrated circuit, the interconnect circuitry connecting the sensor to one or more core devices configured to process the message. The method further includes calculating a first hash value for the first message and comparing the first hash value to one or more prior hash values stored in a hash store, wherein each prior hash value corresponds to a message that was read from the interconnect circuitry prior to the first message. The method further includes performing a corrective action when the difference between the first hash value and at least one of the prior hash values stored in the hash store is above a predetermined threshold.
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公开(公告)号：US20240337693A1
公开(公告)日：2024-10-10
申请号：US18713259
申请日：2021-12-07
IPC分类号： G01R31/3185
CPC分类号： G01R31/318547 , G01R31/318563
摘要： A circuit comprises: scan chains comprising scan cells, the scan chains configured to shift in test patterns, apply the test patterns to the circuit, capture test responses of the circuit, and shift out the test responses; a decompressor configured to decompress compressed test patterns into the test patterns; and a test response compactor configured to compact the test responses, the test response compactor comprising: first X-masking circuitry configured to mask, based on first masking information, some of X bits in the test responses, the first masking information remaining the same while a test response for each of the test patterns is being shifted out, the first masking information being different for at least two of the test patterns; and second masking circuitry configured to mask, based on second masking information, rest of the X bits in the test responses.
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公开(公告)号：US20240288319A1
公开(公告)日：2024-08-29
申请号：US18681795
申请日：2021-08-31
发明人： Gabor Farkas , Zoltan Sarkany
IPC分类号： G01K7/01 , H03K17/687
CPC分类号： G01K7/01 , H03K17/687
摘要： A method of measuring the junction temperature, Tj, of a semiconductor switching element in real-time, and a device for carrying out such a measurement are described. A plurality of measurements of a first and a second, different, temperature-sensitive parameter (TSP) of the semiconductor switching element while recording other quantities determining the semiconductor switching element operating point is taken. The junction temperature value based on the measured values of the first temperature-sensitive parameter and the at least one second temperature-sensitive parameter are calculated and compared to determine the actual junction temperature Tj. Each of the plurality of measurements of the first temperature-sensitive parameter and the at least one second temperature-sensitive parameter is synchronized with a switching event of the semiconductor switching element.
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4.发明公开公开(公告)号：US20240242438A1
公开(公告)日：2024-07-18
申请号：US18558511
申请日：2021-05-08
发明人： Guo Li , Liao Huang , Zhuyu Jin , Feng Yu
CPC分类号： G06T17/20 , G06T7/12 , G06T7/60 , G06T2210/21
摘要： A modeling method for a tubular structure includes: acquiring a structural wire-frame; generating, at each non-manifold node of non-manifold nodes of the structural wire-frame, a polyhedral structure formed by faces of a polyhedron; generating, at each manifold node of manifold nodes of the structural wire-frame, a connecting face; generating, at each end node of end nodes of the structural wire-frame, an end face; connecting vertices of the connecting wire-frame, vertices of the connecting face, and vertices of the end face; and carrying out curved-surface subdivision.
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5.发明公开公开(公告)号：US20240232495A1
公开(公告)日：2024-07-11
申请号：US18002110
申请日：2020-07-08
发明人： Yuansheng Ma , Le Hong
IPC分类号： G06F30/392
CPC分类号： G06F30/392
摘要： A method may include the steps of accessing an input data set of hotspot locations on manufactured circuits of a circuit design. The hotspot locations may be confirmed through a high precision imaging process from a set of candidate locations of the circuit design determined by a low precision imaging process. The method may further include correlating the hotspot locations to layout data for the circuit design, extracting fragment feature vectors for the hotspot locations from optical proximity correction (OPC) fragments of the layout data, processing the fragment feature vectors, providing the processed fragment feature vectors as a training set for training a machine-learning model, and applying the machine-learning model to down select a different set of candidate locations determined by the low precision imaging process.
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6.发明公开公开(公告)号：US20240232454A9
公开(公告)日：2024-07-11
申请号：US18547400
申请日：2021-02-25
发明人： Gaurav Ameta , Wenjie Yao , Elena Arvanitis
IPC分类号： G06F30/17
CPC分类号： G06F30/17
摘要： A computing system may include a transition generation engine configured to access a computer-aided design (CAD) object comprising an external surface and an internal lattice structure represented through repeating unit cells of a lattice design, the internal lattice structure represented as a signed distance field (SDF). The transition generation engine may generate a transition structure for the CAD object within a transition distance from the external surface, including by applying a secondary SDF to modify a portion of the internal lattice structure within the transition distance from the external surface. The computing system may also include an object processing engine may be configured to process the CAD object comprising the transition structure (230) in support of physical manufacture of the CAD object.
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公开(公告)号：US20240232195A9
公开(公告)日：2024-07-11
申请号：US18546461
申请日：2021-03-24
发明人： Barry Etter
IPC分类号： G06F16/2453
CPC分类号： G06F16/24542 , G06F16/24547
摘要： A computing system may include a database system and an application server. The application server may include a logic packaging engine configured to identify a product at a particular stage of a manufacturing process, extract parameter values for the product, and determine processing logic applicable to the product. The processing logic may be designed to query the product database for the product. The logic packaging engine may also be configured to generate an execution package for the database system to perform the query on the product database, and the execution package can include the parameter values for the product at the particular stage in the manufacturing process and metadata references to corresponding query templates stored on the database system.
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公开(公告)号：US20240193335A1
公开(公告)日：2024-06-13
申请号：US18556207
申请日：2021-05-04
IPC分类号： G06F30/337
CPC分类号： G06F30/337
摘要： This application discloses a computing system implementing a shared management system (340) to distribute virtual product models (343), each corresponding to a shared product model (341) describing a product having an electronic device with multiple printed circuit boards, to multiple printed circuit board layout tools (320-1 to 320-N). The printed circuit board layout tools (320-1 to 320-N) separately modify the corresponding virtual product models (343) to generate layout designs for the multiple print circuit boards and generate at least one system-level design rule describing a physical limitation for the electronic device. The shared management system (340) can update the shared product model (341) based on the modifications to at least one of the virtual product models by the printed circuit board layout tools (320-1 to 320-N), and transmit a notification (347) to at least one of the printed circuit board layout tools when the updated shared product model (341) conflicts with the physical limitation for the electronic device described in the at least one system-level design rule.
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公开(公告)号：US12008300B2
公开(公告)日：2024-06-11
申请号：US17462342
申请日：2021-08-31
发明人： Dominic Don
IPC分类号： G06F30/392 , G06F30/394 , G06N20/00
CPC分类号： G06F30/392 , G06F30/394 , G06N20/00
摘要： This application discloses a computing system to identify net lines corresponding to connections between pins of a source layout design describing a first electronic device and pins of a target layout design describing a second electronic device, scan the net lines in an order selected based, at least in part, on an orientation of the net lines between pins of the source layout design and the pins of the target layout design, identify a plurality of the scanned net lines cross each other, and unravel the crossed net lines by swapping pin assignments of the crossed net lines. The computing system can implement a machine learning algorithm having a first stage to determine a scan order for the net lines and having a second stage to identify the net lines that cross each other and unravel the crossed net lines.
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公开(公告)号：US20240160823A1
公开(公告)日：2024-05-16
申请号：US18552692
申请日：2021-04-14
发明人： Nilanjan Mukherjee , Janusz Rajski , Jerin Joe , Irith Pomeranz
IPC分类号： G06F30/333 , G06F119/02
CPC分类号： G06F30/333 , G06F2119/02
摘要： A first circuit design and a second circuit design are analyzed to determine part of the second circuit design structurally similar to part of the first circuit design. A first set of test patterns for the first circuit design is modified to generate a second set of test patterns for the second circuit design by reusing values of bits in the first set of test patterns associated with the part of the first circuit design as values of bits in the second set of test patterns associated with the part of the second circuit design. Fault simulation is performed on the second circuit design using the second set of test patterns to determine a subset of faults undetectable by the second set of test patterns. Test pattern generation is performed for the subset of faults to generate a third set of test patterns for the second circuit design.
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