NON-RETURN TO ZERO (NRZ) AMPLIFIER SYSTEM

    公开(公告)号:US20250038723A1

    公开(公告)日:2025-01-30

    申请号:US18360488

    申请日:2023-07-27

    Abstract: One example includes an amplifier system. The system includes an input configured to receive an input pulse, a first input path coupled to the input and configured to provide the input pulse to a control node, and a second input path coupled to the input and comprising at least one delay element to provide a delayed version of the input pulse to the control node. The system also includes a first amplifier device comprising the control node and being configured to provide a control flux in response to the input pulse and in response to the delayed version of the input pulse. The system further includes a second amplifier device coupled to the first amplifier device, the second amplifier device being set to a flux state in response to the control flux to provide an output voltage.

    DISTRIBUTION-BASED RISK MANAGEMENT IN CLASSIFICATION MODELS

    公开(公告)号:US20240419989A1

    公开(公告)日:2024-12-19

    申请号:US18393263

    申请日:2023-12-21

    Abstract: Systems and methods are provided for risk management in an expert system. A distribution of feature values within a training dataset for the expert system and each of a plurality of baseline datasets are determined, and Kullback-Leibler divergences between the baseline dataset and the training dataset to provide set of Kullback-Leibler divergence values. Measures of central tendency and statistical dispersion of the set of Kullback-Leibler divergence values are determined, and a threshold Kullback-Leibler divergence value is determined from these values and a desired confidence interval for new datasets. A Kullback-Leibler divergence value between the feature values of novel dataset and the training dataset is determined and it is determined that the second dataset represents an unacceptable divergence if this Kullback-Leibler divergence value exceeds the threshold value.

    LOW POWER PHASE DETECTOR
    6.
    发明申请

    公开(公告)号:US20240402231A1

    公开(公告)日:2024-12-05

    申请号:US18328879

    申请日:2023-06-05

    Abstract: Phase detectors are provided. In one example, The phase detector may include a first transistor leg and a second transistor leg. Each of the first transistor leg and the second transistor leg may include a pair of transistors coupled together at a plurality of common nodes. The phase detector may include an input at the first transistor leg. The input may be configured to receive a first input signal and a second input signal. The phase detect may include an output coupled to the second transistor leg. The output may be configured to provide an output signal. The output signal may include a component indicative of a phase difference between the first input signal and the second input signal.

    Channelized filter using semiconductor fabrication

    公开(公告)号:US12119313B2

    公开(公告)日:2024-10-15

    申请号:US18382598

    申请日:2023-10-23

    CPC classification number: H01L23/66 H01P1/20327 H01L2223/6627 H01L2223/6655

    Abstract: A semiconductor technology implemented high-frequency channelized filter includes a dielectric substrate with metal traces disposed on one of two major surfaces of the substrate. An input and output port disposed on the substrate and one of the metal traces carrying a high-frequency signal to be filtered between the input and output port. Other of the metal traces are connected to the one metal trace at intervals along the length of the one metal trace each providing a reactance to the high-frequency signal where the reactance varies with frequency and additional traces of the metal traces serving as a reference ground for the one metal trace and the other metal traces. A silicon enclosure mounted to the substrate with a first planar surface with cavities in the enclosure that extend through the first surface, and internal walls within the silicon enclosure defining the cavities. A layer of conductive metal covers the first planar surface, cavities and the internal walls. The silicon enclosure having substantially continuous areas of metal on the first planar surface about the periphery of the silicon enclosure that engage corresponding areas of the additional traces about the periphery of the substrate. The cavities surround the respective other metal traces with the internal cavity walls engaging the additional traces adjacent the respective other metal traces to individually surround each of the other metal traces with a conductive metal thereby providing electromagnetic field isolation between each of the other metal traces.

    DEPLOYABLE PANEL ARRAY AND RELATED ASSEMBLIES AND METHODS

    公开(公告)号:US20240300673A1

    公开(公告)日:2024-09-12

    申请号:US17571369

    申请日:2022-01-07

    CPC classification number: B64G1/222 B64G1/10 B64G1/42

    Abstract: A panel array and associated deployment system may include a first cable extending along a first row of panels and coupled to each panel of the first row of panels. The array and system may further include a second cable extending along a second row of panels and coupled to each panel of the second row of panels. The array and system may also include a first column of panels comprising a panel from the first row of panels and a panel from the second row of panels. The system may further include a spool positioned adjacent the first column of panels. The spool may be coupled to at least one of the first cable and the second cable and configured to apply tension to the first cable and/or the second cable.

    SYSTEMS AND METHODS FOR MEASURING CHARACTERISTICS OF CRYOGENIC ELECTRONIC DEVICES

    公开(公告)号:US20240255558A1

    公开(公告)日:2024-08-01

    申请号:US18630577

    申请日:2024-04-09

    CPC classification number: G01R27/16

    Abstract: This disclosure relates to systems and methods for measuring impedance characteristics of a cryogenic device under test (DUT). A channel select circuit can be configured in a first state to electrically isolate a channel output circuit from the cryogenic DUT and in a second state to electrically couple the channel output circuit to the cryogenic DUT, and at least one resistor can be positioned along a transmission path that couples a pattern generator circuit to a channel output circuit that includes the channel select circuit. A controller can be configured to cause respective test current signals to be provided along the transmission path when the channel select circuit is in respective first and second states to establish respective first and second voltages across the at least one resistor, determine first and second impedance characteristics of the transmission path for determining an impedance of the cryogenic DUT.

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