公开(公告)号：US08717060B2

公开(公告)日：2014-05-06

申请号：US13275721

申请日：2011-10-18

Applicant: Jung Hee Lee

Inventor： Jung Hee Lee

IPC: G01R31/02 ,  G01R31/3187

CPC classification number: G01R31/2601 ,  H03F1/30 ,  H03F2200/447

Abstract: An integrated circuit includes a process sensor, a temperature sensor, and a voltage sensor. The process sensor is configured to sense a process parameter indicative of a semiconductor process by which the integrated circuit is formed and, based upon the sensed process parameter, to provide a characterization of the semiconductor process to the output of the process sensor. The temperature sensor is configured to provide an indication of a temperature of the integrated circuit to an output of the temperature sensor and the voltage sensor is configured to provide an indication of a power supply voltage level of the integrated circuit to an output of the voltage sensor. The output of the process sensor is coupled to at least one of the temperature sensor and the voltage sensor to compensate at least one of the indication of the temperature and the indication of the power supply voltage level.

Abstract translation: 集成电路包括过程传感器，温度传感器和电压传感器。 过程传感器被配置为感测指示形成集成电路的半导体工艺的工艺参数，并且基于所感测的工艺参数，以提供对工艺传感器的输出的半导体工艺的表征。 温度传感器被配置为提供集成电路的温度到温度传感器的输出的指示，并且电压传感器被配置为提供集成电路的电源电压电平到电压传感器的输出的指示 。 过程传感器的输出耦合到温度传感器和电压传感器中的至少一个，以补偿温度指示和电源电压电平指示中的至少一个。

公开(公告)号：US20140111234A1

公开(公告)日：2014-04-24

申请号：US13656761

申请日：2012-10-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Peter Laackmann ,  Marcus Janke

IPC: G01R31/3187 ,  H01L21/50 ,  H01L23/544

CPC classification number: G01R31/31719 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In various embodiments, a die is provided. The die may include a physical unclonable function circuit configured to provide an output signal, wherein the output signal is dependent on at least one physical characteristic specific to the die; and a self-test circuit integrated with the physical unclonable function circuit on the die, wherein the self-test circuit is configured to provide at least one test input signal to the physical unclonable function circuit and to determine as to whether the output signal provided in response to the at least one test input signal fulfills a predefined criterion.

Abstract translation: 在各种实施例中，提供了一个模具。 芯片可以包括被配置为提供输出信号的物理不可克隆功能电路，其中输出信号取决于芯片特有的至少一个物理特性; 以及与所述管芯上的所述物理不可克隆功能电路集成的自检电路，其中所述自检电路被配置为向所述物理不可克隆功能电路提供至少一个测试输入信号，并且确定所提供的输出信号是否 对至少一个测试输入信号的响应满足预定义的标准。

公开(公告)号：US08659310B2

公开(公告)日：2014-02-25

申请号：US13087550

申请日：2011-04-15

Applicant: Martin Eckert ,  Roland Frech ,  Jochen Supper ,  Otto A. Torreiter

Inventor： Martin Eckert ,  Roland Frech ,  Jochen Supper ,  Otto A. Torreiter

IPC: G01R31/3187

CPC classification number: G01R31/31721 ,  G01R31/3004

Abstract: A method and system for performing a self-test of power supply quality for an integrated circuit chip within an electronic system. The electronic system is subjected to a well-defined repetitive activity, such as by using an amplitude modulated system clock tree. With the repetitive activity causing current consumption within the chip, time-domain local power supply voltage (U(t)) is measured for a location on the chip. A set of time-domain measured voltage data (U(t)) is accumulated and transformed into the frequency domain to yield a local voltage profile (U(f)). The local voltage profile (U(f)) is compared with a reference voltage profile (U0(f)) to verify whether power supply quality at the chip location under test is adequate. Alternatively, a local impedance profile Z(f) evaluated from the local voltage profile (U(f)) may be compared to a reference impedance profile Z0(f).

Abstract translation: 一种用于对电子系统内的集成电路芯片进行电源质量自检的方法和系统。 电子系统受到明确的重复活动，例如通过使用调幅系统时钟树。 由于重复的活动导致芯片内的电流消耗，对于芯片上的位置测量时域本地电源电压（U（t））。 一组时域测量电压数据（U（t））被积累并变换到频域以产生局部电压分布（U（f））。 将本地电压曲线（U（f））与参考电压曲线（U0（f））进行比较，以验证被测芯片位置的电源质量是否足够。 或者，可以将从局部电压分布（U（f））估计的局部阻抗曲线Z（f）与参考阻抗曲线Z0（f）进行比较。

公开(公告)号：US08633723B2

公开(公告)日：2014-01-21

申请号：US13024669

申请日：2011-02-10

Applicant: Shigeyuki Takeuchi

Inventor： Shigeyuki Takeuchi

IPC: G01R31/3187

CPC classification number: H01L29/7815 ,  H01L27/088 ,  H01L29/0696 ,  H01L29/7397 ,  H01L29/7803 ,  H01L29/7813 ,  H01L29/7831 ,  H03K17/0822 ,  H03K17/122 ,  H03K2217/0027

Abstract: A semiconductor apparatus according to aspects of the invention includes a power MOSFET including a main MOSFET and sensing MOSFET's. The main MOSFET and the sensing MOSFET's are formed on a semiconductor substrate, and a sensing MOSFET is selected for changing the sensing ratio and further for confining the sensing ratio variations within a certain narrow range stably from a low main current range to a high main current range. A semiconductor apparatus according to aspects of the invention facilitates reducing the manufacturing costs thereof, obviating the cumbersomeness caused in the use thereof, and confining the sensing ratio variations within a certain narrow range stably.

Abstract translation: 根据本发明的方面的半导体装置包括功率MOSFET，其包括主MOSFET和感测MOSFET。 主MOSFET和感测MOSFET形成在半导体衬底上，并且选择感测MOSFET用于改变感测比率，并且进一步将感测比变化限制在一定窄范围内，从低主电流范围稳定到高主电流 范围。 根据本发明的方面的半导体装置有助于降低其制造成本，从而避免了在使用中引起的麻烦，并且将感测比变化限制在一定的窄范围内。

公开(公告)号：US08633722B1

公开(公告)日：2014-01-21

申请号：US12894026

申请日：2010-09-29

Applicant: Andrew W. Lai

Inventor： Andrew W. Lai

IPC: G01R31/3187 ,  G01R31/20 ,  H03K25/00 ,  G01R31/28

CPC classification number: G01R31/2882 ,  G01R31/31725 ,  H03K19/17764 ,  H03K23/425

Abstract: In one embodiment a circuit for testing delays is provided. A test signal generator circuit toggles a plurality of output signals 1 through N in sequential order, separating the toggles by a delay period. Each output signal is coupled to an input of a respective one of a plurality of delay circuits. A phase detector circuit is coupled to the delay circuits and is configured to determine the order in which signals output from delay circuits X−1, X, and X+1 are toggled for each delay circuit X. In response to the output signals being toggled in the order X−1 followed by X followed by X+1, the phase comparator circuit is configured to output a first signal indicating correct operation. Otherwise, the phase comparator circuit is configured to output a second signal indicating incorrect operation.

Abstract translation: 在一个实施例中，提供了用于测试延迟的电路。 测试信号发生器电路按顺序切换多个输出信号1至N，将切换分开延迟时间。 每个输出信号耦合到多个延迟电路中的相应一个的输入。 相位检测器电路被耦合到延迟电路，并且被配置为确定从延迟电路X-1，X和X + 1输出的信号针对每个延迟电路X切换的顺序。响应于输出信号被切换 按照X-1之后的X，随后是X + 1，相位比较器电路被配置为输出指示正确操作的第一信号。 否则，相位比较器电路被配置为输出指示不正确操作的第二信号。

公开(公告)号：US08598900B2

公开(公告)日：2013-12-03

申请号：US13572774

申请日：2012-08-13

Applicant: Xia Xu ,  Wen-Ming Yi ,  Yu-Lin Liu

Inventor： Xia Xu ,  Wen-Ming Yi ,  Yu-Lin Liu

IPC: G01R31/3187

CPC classification number: G01R31/317 ,  G01R31/31721

Abstract: A system for testing electronic device includes an electronic device, a temperature detecting module, a testing instrument and a testing computer. The testing electronic includes a main board and a power supply. The main board includes a slot and a card inserted in the slot. A plurality of dummy loads is located on the card. The slot includes at least one voltage interface. The power supply includes at least one power wire electrically connected to the at least one voltage interface. The temperature detecting module detects temperature signals of the plurality of dummy loads. The testing instrument is electrically connected to the at least one power wire to test current signals or power signals of the at least one power wire. The testing computer receives and displays the temperature signals, the current signals and the power signals.

Abstract translation: 一种用于电子设备测试的系统包括电子设备，温度检测模块，测试仪器和测试计算机。 测试电子包括主板和电源。 主板包括插槽和插入插槽中的卡。 多个虚拟负载位于卡上。 该插槽包括至少一个电压接口。 电源包括电连接到至少一个电压接口的至少一个电源线。 温度检测模块检测多个虚拟负载的温度信号。 所述测试仪器电连接到所述至少一个电源线以测试所述至少一根电源线的当前信号或功率信号。 测试电脑接收并显示温度信号，电流信号和电源信号。

公开(公告)号：US08564318B2

公开(公告)日：2013-10-22

申请号：US13830771

申请日：2013-03-14

Applicant: Renesas Electronics Corporation

Inventor： Shinya Tashiro ,  Kazutaka Taniguchi

IPC: G01R31/3187

CPC classification number: H03K3/356008 ,  G01R19/0084 ,  G01R31/2884

Abstract: A semiconductor device includes a power-supply circuit which produces a first voltage potential, a first terminal, a second terminal which receives a mode signal, an inverter which receives the mode signal and outputs an inverted mode signal, and a first transfer circuit which includes a first transistor of a first conductivity type and a second transistor of a second conductivity type, the first transistor coupled between the power-supply circuit and a first node, the second transistor coupled between the power-supply circuit and the first node in parallel with the first transistor, a control gate of the first transistor supplied with the inverted mode signal and a control gate of the second transistor supplied with the mode signal.

Abstract translation: 一种半导体器件包括产生第一电压电位的电源电路，第一端子，接收模式信号的第二端子，接收模式信号并输出​​反相模式信号的反相器，以及第一传输电路，其包括 第一导电类型的第一晶体管和第二导电类型的第二晶体管，所述第一晶体管耦合在所述电源电路和第一节点之间，所述第二晶体管耦合在所述电源电路和所述第一节点之间并联 第一晶体管，提供有反相模式信号的第一晶体管的控制栅极和提供有模式信号的第二晶体管的控制栅极。

公开(公告)号：US20130265066A1

公开(公告)日：2013-10-10

申请号：US13539486

申请日：2012-07-01

Applicant: Chih-Cheng Hsieh ,  Shang-Fu Yeh ,  Ka-Yi Yeh

Inventor： Chih-Cheng Hsieh ,  Shang-Fu Yeh ,  Ka-Yi Yeh

IPC: G01R31/3187

CPC classification number: G01R31/3187 ,  G02F1/00 ,  G02F2001/136254 ,  H04N1/00 ,  H04N5/367 ,  H04N17/002 ,  H04N2101/00 ,  H04N2201/00

Abstract: A pixel array module with a self-test function including a test circuit unit, a plurality of test lines, and a pixel array is provided. The test circuit unit provides the self-test function. The test lines are connected between the test circuit unit and the pixel array. The pixel array is connected to the test circuit unit through the test lines and includes a plurality of pixels. Each pixel includes a transistor. Each transistor has a first terminal and a second terminal. Regarding each of the pixels, a driving signal of the transistor is transmitted from the first terminal to the second terminal thereof under a normal mode, and a test signal of the transistor is transmitted from the second terminal to the first terminal thereof under a test mode. Furthermore, a self-test method of the foregoing pixel array module is also provided.

Abstract translation: 提供具有包括测试电路单元，多个测试线和像素阵列的自检功能的像素阵列模块。 测试电路单元提供自检功能。 测试线连接在测试电路单元和像素阵列之间。 像素阵列通过测试线连接到测试电路单元，并且包括多个像素。 每个像素包括晶体管。 每个晶体管具有第一端子和第二端子。 关于每个像素，晶体管的驱动信号在正常模式下从第一端子传输到其第二端子，并且在测试模式下将晶体管的测试信号从第二端子传输到其第一端子 。 此外，还提供了上述像素阵列模块的自检方法。

公开(公告)号：US20130241586A1

公开(公告)日：2013-09-19

申请号：US13881106

申请日：2010-12-09

Applicant: Tomo Horikawa ,  Kunio Ooba ,  Taku Watanabe

Inventor： Tomo Horikawa ,  Kunio Ooba ,  Taku Watanabe

IPC: G01R31/3187

CPC classification number: G01R31/3187 ,  G05B23/0267

Abstract: An industrial automatic-diagnostic device connected to an FA system in which a plurality of FA devices are connected to each other, the industrial automatic-diagnostic device includes: an engineering tool; and a display unit. Based on interface connection information and device configuration information of a corresponding FA device held by each of the FA devices, the engineering tool creates overall configuration information of the FA system and displays an overall configuration of the FA system on the display unit based on the overall configuration information. When an abnormality occurs in the FA device, diagnosis information about an abnormal part self-diagnosed by the FA device and abnormality contents with respect to the abnormality occurred in a corresponding abnormal part is obtained. Based on the obtained diagnosis information, occurrence of an abnormality is displayed in an abnormal part in an overall configuration of the FA system displayed on the display unit.

Abstract translation: 一种工业自动诊断装置，其与多个FA装置相互连接的FA系统连接，所述工业自动诊断装置包括：工程工具; 和显示单元。 基于由FA设备保持的对应的FA设备的接口连接信息和设备配置信息，工程工具创建FA系统的整体配置信息，并且基于总体上的显示单元显示FA系统的整体配置 配置信息。 当在FA装置发生异常时，获得关于由FA装置自身诊断的异常部分的诊断信息和相应的异常部分发生的相对于异常的异常内容。 基于所获得的诊断信息，在显示单元上显示的FA系统的整体结构中的异常部分中显示异常的发生。

公开(公告)号：US20130154677A1

公开(公告)日：2013-06-20

申请号：US13332285

申请日：2011-12-20

Applicant: Linda K. Sun ,  Harry Muljono

Inventor： Linda K. Sun ,  Harry Muljono

IPC: G01R31/3187

CPC classification number: G01R31/2853 ,  G01N27/228 ,  G01R31/2884 ,  H01L22/34

Abstract: A pad capacitance test circuit may be coupled to one or more pads of an electronic circuit, such as a processor. The pad capacitance test circuit may be located on a die including the electronic circuit. The pad capacitance test circuit may reset a pad voltage of one or more of the pads to zero, and then couple the pad to a supply voltage through a pullup resistor for a time period. The final pad voltage at or near the end of the period of time may be measured. The pad capacitance may be determined from the measured value of the final pad voltage and known values of the supply voltage, the time period, and resistance of the pullup resistor.