Abstract:
An integrated circuit includes a process sensor, a temperature sensor, and a voltage sensor. The process sensor is configured to sense a process parameter indicative of a semiconductor process by which the integrated circuit is formed and, based upon the sensed process parameter, to provide a characterization of the semiconductor process to the output of the process sensor. The temperature sensor is configured to provide an indication of a temperature of the integrated circuit to an output of the temperature sensor and the voltage sensor is configured to provide an indication of a power supply voltage level of the integrated circuit to an output of the voltage sensor. The output of the process sensor is coupled to at least one of the temperature sensor and the voltage sensor to compensate at least one of the indication of the temperature and the indication of the power supply voltage level.
Abstract:
In various embodiments, a die is provided. The die may include a physical unclonable function circuit configured to provide an output signal, wherein the output signal is dependent on at least one physical characteristic specific to the die; and a self-test circuit integrated with the physical unclonable function circuit on the die, wherein the self-test circuit is configured to provide at least one test input signal to the physical unclonable function circuit and to determine as to whether the output signal provided in response to the at least one test input signal fulfills a predefined criterion.
Abstract:
A method and system for performing a self-test of power supply quality for an integrated circuit chip within an electronic system. The electronic system is subjected to a well-defined repetitive activity, such as by using an amplitude modulated system clock tree. With the repetitive activity causing current consumption within the chip, time-domain local power supply voltage (U(t)) is measured for a location on the chip. A set of time-domain measured voltage data (U(t)) is accumulated and transformed into the frequency domain to yield a local voltage profile (U(f)). The local voltage profile (U(f)) is compared with a reference voltage profile (U0(f)) to verify whether power supply quality at the chip location under test is adequate. Alternatively, a local impedance profile Z(f) evaluated from the local voltage profile (U(f)) may be compared to a reference impedance profile Z0(f).
Abstract:
A semiconductor apparatus according to aspects of the invention includes a power MOSFET including a main MOSFET and sensing MOSFET's. The main MOSFET and the sensing MOSFET's are formed on a semiconductor substrate, and a sensing MOSFET is selected for changing the sensing ratio and further for confining the sensing ratio variations within a certain narrow range stably from a low main current range to a high main current range. A semiconductor apparatus according to aspects of the invention facilitates reducing the manufacturing costs thereof, obviating the cumbersomeness caused in the use thereof, and confining the sensing ratio variations within a certain narrow range stably.
Abstract:
In one embodiment a circuit for testing delays is provided. A test signal generator circuit toggles a plurality of output signals 1 through N in sequential order, separating the toggles by a delay period. Each output signal is coupled to an input of a respective one of a plurality of delay circuits. A phase detector circuit is coupled to the delay circuits and is configured to determine the order in which signals output from delay circuits X−1, X, and X+1 are toggled for each delay circuit X. In response to the output signals being toggled in the order X−1 followed by X followed by X+1, the phase comparator circuit is configured to output a first signal indicating correct operation. Otherwise, the phase comparator circuit is configured to output a second signal indicating incorrect operation.
Abstract:
A system for testing electronic device includes an electronic device, a temperature detecting module, a testing instrument and a testing computer. The testing electronic includes a main board and a power supply. The main board includes a slot and a card inserted in the slot. A plurality of dummy loads is located on the card. The slot includes at least one voltage interface. The power supply includes at least one power wire electrically connected to the at least one voltage interface. The temperature detecting module detects temperature signals of the plurality of dummy loads. The testing instrument is electrically connected to the at least one power wire to test current signals or power signals of the at least one power wire. The testing computer receives and displays the temperature signals, the current signals and the power signals.
Abstract:
A semiconductor device includes a power-supply circuit which produces a first voltage potential, a first terminal, a second terminal which receives a mode signal, an inverter which receives the mode signal and outputs an inverted mode signal, and a first transfer circuit which includes a first transistor of a first conductivity type and a second transistor of a second conductivity type, the first transistor coupled between the power-supply circuit and a first node, the second transistor coupled between the power-supply circuit and the first node in parallel with the first transistor, a control gate of the first transistor supplied with the inverted mode signal and a control gate of the second transistor supplied with the mode signal.
Abstract:
A pixel array module with a self-test function including a test circuit unit, a plurality of test lines, and a pixel array is provided. The test circuit unit provides the self-test function. The test lines are connected between the test circuit unit and the pixel array. The pixel array is connected to the test circuit unit through the test lines and includes a plurality of pixels. Each pixel includes a transistor. Each transistor has a first terminal and a second terminal. Regarding each of the pixels, a driving signal of the transistor is transmitted from the first terminal to the second terminal thereof under a normal mode, and a test signal of the transistor is transmitted from the second terminal to the first terminal thereof under a test mode. Furthermore, a self-test method of the foregoing pixel array module is also provided.
Abstract:
An industrial automatic-diagnostic device connected to an FA system in which a plurality of FA devices are connected to each other, the industrial automatic-diagnostic device includes: an engineering tool; and a display unit. Based on interface connection information and device configuration information of a corresponding FA device held by each of the FA devices, the engineering tool creates overall configuration information of the FA system and displays an overall configuration of the FA system on the display unit based on the overall configuration information. When an abnormality occurs in the FA device, diagnosis information about an abnormal part self-diagnosed by the FA device and abnormality contents with respect to the abnormality occurred in a corresponding abnormal part is obtained. Based on the obtained diagnosis information, occurrence of an abnormality is displayed in an abnormal part in an overall configuration of the FA system displayed on the display unit.
Abstract:
A pad capacitance test circuit may be coupled to one or more pads of an electronic circuit, such as a processor. The pad capacitance test circuit may be located on a die including the electronic circuit. The pad capacitance test circuit may reset a pad voltage of one or more of the pads to zero, and then couple the pad to a supply voltage through a pullup resistor for a time period. The final pad voltage at or near the end of the period of time may be measured. The pad capacitance may be determined from the measured value of the final pad voltage and known values of the supply voltage, the time period, and resistance of the pullup resistor.