公开(公告)号：US4989135A

公开(公告)日：1991-01-29

申请号：US534350

申请日：1990-06-05

申请人： Sakae Miki

发明人： Sakae Miki

IPC分类号： H04L29/10 ,  G06F13/00 ,  G06F13/42

CPC分类号： G06F13/4204

摘要： Disclosed is a communication control microcomputer which includes components that implement serial communication control in compliance with a communication protocol, a FIFO memory for temporarily holding transaction data, a direct memory access control (DMAC) for implementing DMA transfer between the FIFO memory and the main memory, and a CPU for implementing general control over these components. A signal indicating end of frame (transaction data) is passed between components that control the serial communication and the DMAC through the FIFO memory.

摘要翻译： 公开了一种通信控制微计算机，其包括根据通信协议实现串行通信控制的组件，用于临时保存事务数据的FIFO存储器，用于在FIFO存储器和主存储器之间实现DMA传输的直接存储器访问控制（DMAC） ，以及用于实现对这些组件的一般控制的CPU。 指示帧结束的信号（事务数据）在控制串行通信的组件和通过FIFO存储器的DMAC之间传递。

公开(公告)号：US4859815A

公开(公告)日：1989-08-22

申请号：US285921

申请日：1988-12-19

申请人： John W. Irwin ,  James D. Wagoner

发明人： John W. Irwin ,  James D. Wagoner

IPC分类号： H04L29/10 ,  H04L1/00 ,  H04L25/49

CPC分类号： H04L25/4906 ,  H04L1/0083

摘要： In a serial link in which it is necessary to occupy the link before and after transmission of a frame by sending a succession idle characters having alternating disparity effects, the disparity effect of the last character in the frame is compared with the disparity effect that would be produced by a disparity flip-flop, which has continued to step during frame transmission. If the disparity effect of these two characters match, no corrective action is required in order to resume the stream of idle characters. If the disparity effect of these characters differ, the disparity flip-flop is corrected before the stream of idle characters is resumed. Disclosed is hardware logic to accomplish this disparity control following transmission of frames in a transparent mode.

公开(公告)号：US4807282A

公开(公告)日：1989-02-21

申请号：US814436

申请日：1985-12-30

申请人： Howard Kazan ,  Ronald W. Kohake

发明人： Howard Kazan ,  Ronald W. Kohake

IPC分类号： H04L29/06 ,  G06F13/38 ,  H04L29/10 ,  G06F9/00

CPC分类号： G06F13/387

摘要： A multi-protocol communications adapter (MPCA) is used to interconnect a Local Area Network (such as a store computing system) to a communications highway. The MPCA includes a plurality of protocol controllers, each one of the controllers being operable for converting a data stream into a predetermined format. A programmable configuration register is provided for selecting one of the protocol controllers. A controlled interface is provided for gating the selected controller onto the communications highway. The MPCA is packaged as a card or module. It is coupled to a primary computer that controls the Local Area Network. The primary computer may effectuate a protocol change by changing the contents of the configuration register. Thus, the MPCA can be used with a pre-existing primary computer without significantly changing the architecture and/or programming of said computer.

摘要翻译： 多协议通信适配器（MPCA）用于将局域网（例如商店计算系统）与通信公路相互连接。 MPCA包括多个协议控制器，每个控制器可操作用于将数据流转换成预定格式。 提供可编程配置寄存器用于选择一个协议控制器。 提供控制接口以将所选择的控制器门控到通信高速公路上。 MPCA作为卡或模块打包。 它耦合到控制局域网的主计算机。 主计算机可以通过改变配置寄存器的内容来实现协议更改。 因此，MPCA可以与预先存在的主计算机一起使用，而不会显着地改变所述计算机的架构和/或编程。

公开(公告)号：US4734908A

公开(公告)日：1988-03-29

申请号：US926012

申请日：1986-10-31

申请人： Kurt A. Hedlund

发明人： Kurt A. Hedlund

IPC分类号： H04L29/02 ,  H04L12/64 ,  H04L29/10 ,  H04Q11/04

CPC分类号： H04L12/64

摘要： A digital trunk interface utilizing the first protocol handler to signal the start of a packet and a second protocol handler responsive to the packet delayed to initiate the storage of the packet internally to the digital trunk interface. The digital trunk interface comprises a microprocessor and two universal synchronous asynchronous receiver transmitter (USART) circuits. One USART is directly connected to the incoming digital trunk and is utilized to inform the microprocessor when a packet is first received. The second USART receives the packet delayed by a predefined amount of time from the digital trunk. The microprocessor is responsive to the signal from the first USART that a packet has been received to perform the necessary administrative functions for receipt of the packet by the second USART.

摘要翻译： 一个数字中继接口，利用第一协议处理器来发信号通知分组的起点，以及一个响应分组的第二协议处理器，该分组被延迟以发起分组在内部存储到数字中继接口。 数字中继接口包括微处理器和两个通用同步异步接收发射机（USART）电路。 一个USART直接连接到输入数字中继线，并且用于在首次接收到分组时通知微处理器。 第二个USART从数字中继线接收延迟了预定义时间的数据包。 微处理器响应来自第一USART的信号已经接收到分组以执行必要的管理功能，以便由第二USART接收分组。

公开(公告)号：US4577327A

公开(公告)日：1986-03-18

申请号：US656761

申请日：1984-10-01

申请人： Shigeo Nambu

发明人： Shigeo Nambu

IPC分类号： H04L29/10 ,  H04L5/14 ,  H04L5/16

CPC分类号： H04L5/16 ,  H04L5/1461

摘要： A repeater for a transmission system which can pass signals in either of two directions. Each direction has a signal detection circuit associated with it. Upon detection of the beginning of a signal, the signal detection circuit enables an associated driver to pass the signal in the appropriate direction and at the same time disables the other signal detection circuit so that a signal will pass in only one direction at a time. An end flag detecting circuit monitors for certain characteristics associated with the end of the signal, and upon detection causes both drivers to be disabled and both signal detection circuits to be reset so that they can again detect a signal passing in either direction.

摘要翻译： 用于传输系统的中继器，其可以在两个方向中的任一个传递信号。 每个方向都有一个信号检测电路。 在检测到信号的开始时，信号检测电路使得​​相关联的驱动器能够以适当的方向传递信号，并且同时禁用另一个信号检测电路，使得信号一次只能通过一个方向。 结束标志检测电路监测与信号结束相关的特定特性，并且在检测到时，两个驱动器被禁用，并且两个信号检测电路都被复位，使得它们可以再次检测在任一方向上通过的信号。

公开(公告)号：US4482955A

公开(公告)日：1984-11-13

申请号：US568513

申请日：1984-01-09

申请人： Katsumi Amano ,  Takatoshi Ishii

发明人： Katsumi Amano ,  Takatoshi Ishii

IPC分类号： G06F3/02 ,  G06F13/00 ,  H04L29/10 ,  G06F1/00

CPC分类号： G06F3/0227

摘要： A data transfer system in which a data entry system is converted from manual operation to automatic reading in a computer system, thereby to save time in the inputting of data into the computer system. The data entry system includes a main processor having a central processing unit (CPU) and a keyboard unit including a microprocessor. Provision of the microprocessor at the keyboard enables physical separation of the keyboard unit from the CPU by means of only a single bi-directional cable. The CPU periodically sends polling data in serial data format via the bi-directional cable to the keyboard microprocessor, which then controls a keyboard matrix scanning operation in performing the commands represented by the polling data. The microprocessor then controls serial transmission of keyboard data to the CPU via the bi-directional cable. Thus the data transfer system is suitable for high performance data transfer between the CPU of the main processor and the microprocessor of the keyboard unit.

摘要翻译： 一种数据传输系统，其中数据输入系统从手动操作转换为计算机系统中的自动读取，从而节省将数据输入计算机系统的时间。 数据输入系统包括具有中央处理单元（CPU）和包括微处理器的键盘单元的主处理器。 在键盘上提供微处理器可以通过仅一根双向电缆实现键盘单元与CPU的物理分离。 CPU通过双向电缆将串行数据格式的轮询数据周期性地发送到键盘微处理器，然后键盘微处理器执行键盘矩阵扫描操作，执行由轮询数据表示的命令。 然后微处理器通过双向电缆控制键盘数据到CPU的串行传输。 因此，数据传输系统适用于主处理器的CPU和键盘单元的微处理器之间的高性能数据传输。

公开(公告)号：US11949744B2

公开(公告)日：2024-04-02

申请号：US17717351

申请日：2022-04-11

申请人： Google LLC

发明人： Yuewei Wang ,  Shashank Chaudhary ,  Onur Soysal ,  Michael Ortega-Binderberger

IPC分类号： H04L15/16 ,  G06F15/16 ,  G06F21/31 ,  H04L9/40 ,  H04L29/06 ,  H04L29/08 ,  H04L29/10 ,  H04L67/02 ,  H04L67/14

CPC分类号： H04L67/14 ,  G06F21/31 ,  H04L63/10 ,  H04L67/02

摘要： Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for enhancing online user privacy. Methods can include receiving tag information specifying a given publisher identifier for a publisher and a given client identifier assigned to a user of the client device by the publisher. A given service identifier assigned to the user by the service apparatus is obtained. A mapping between the given service identifier to the given client identifier is created. A list of client identifiers assigned to a set of users by the publisher is received. A list of matched service identifiers corresponding to the list of client identifiers are stored. Multiple content requests are received from multiple different client devices accessing services provided by the service apparatus. Responses to the content requests are based on whether the client devices provide service identifiers that are included in the list of matched service identifiers.

公开(公告)号：US11023515B2

公开(公告)日：2021-06-01

申请号：US15780232

申请日：2016-11-30

申请人： Faraday & Future Inc.

发明人： Nicholas William Dazé ,  Matthew Joseph Coburn ,  Eric Ryan Evenchick ,  Sethu Hareesh Kolluru ,  Luke Michael Ekkizogloy ,  Carlos John Rosario ,  Xiufeng Song

IPC分类号： A63F13/25 ,  G06F16/435 ,  G06F16/44 ,  H04L29/08 ,  G01C21/36 ,  H04L29/10 ,  H04L12/40 ,  A63F13/90 ,  G01C21/34 ,  G09B5/06 ,  G06F3/0481

摘要： A system for providing media content to an occupant of a vehicle may include a user interface configured to provide the media content to the occupant and a controller coupled to the user interface and to a database configured to store media content. The controller may be configured to receive vehicle navigation data, select a subset of media content from the media content stored in the database based on the vehicle navigation data, and provide the subset of media content through the user interface.

公开(公告)号：US10986171B2

公开(公告)日：2021-04-20

申请号：US16548574

申请日：2019-08-22

申请人： Huawei Technologies Co., Ltd.

发明人： Lin Peng

IPC分类号： H04L29/10 ,  H04L29/08 ,  H04L12/24 ,  H04L12/933 ,  H04L12/931 ,  G06F3/14 ,  H04L12/721

摘要： In a method for unified communication of a server, a baseboard management controller (BMC) receives a first packet sent by a server, and forwards the received first packet to a physical network adapter of the BMC using a preconfigured virtual network adapter, where the first packet includes first management data or service data. The first packet is sent to an external network via the physical network adapter. The virtual network adapter is further configured to send a second packet received by the BMC to a control module of the BMC, and the control module processes the second packet.

公开(公告)号：US20200304425A1

公开(公告)日：2020-09-24

申请号：US16895539

申请日：2020-06-08

申请人： Intel Corporation

发明人： Francesc Guim Bernat ,  Kshitij A. Doshi ,  Daniel Rivas Barragan ,  Alejandro Duran Gonzalez

IPC分类号： H04L12/933 ,  H04L29/10

摘要： Technologies for performing switch-based collective operations in a fabric architecture include a network switch communicatively coupled to a plurality of computing nodes. The network switch is configured to identify sub-operations of a collective operation of a collective operation request received from one of the computing nodes and identify a plurality of operands for each of the sub-operations. The network switch is additionally configured to request a value for each of the operands from a corresponding target computing node at which the respective value is stored, determine a result of the collective operation as a function of the requested operand values, and transmit the result to the requesting computing node. Other embodiments are described herein.