公开(公告)号：US09514080B1

公开(公告)日：2016-12-06

申请号：US14215919

申请日：2014-03-17

申请人： Marvell International Ltd.

发明人： Po-Chien Chang

IPC分类号： G06F13/36 ,  G06F13/38

CPC分类号： G06F13/387 ,  G06F13/36

摘要： An emulation circuit configured to emulate each of a master mode and a slave mode to provide an interface between a host device and a plurality of storage devices. The emulation circuit includes a first bus and a second bus. The emulation circuit includes a plurality of bridge circuits each configured to communicate with the host device over the first bus, communicate with a respective storage device of a plurality of storage devices over the second bus, and receive a mode select signal configured to set the bridge circuit to one of a host mode and a device mode. The bridge circuit is further configured to, if the mode select signal sets the bridge circuit to the host mode, select, based on an emulation select signal, between the master mode and the slave mode.

摘要翻译： 一种仿真电路，被配置为模拟主模式和从模式中的每一者以提供主机设备和多个存储设备之间的接口。 仿真电路包括第一总线和第二总线。 仿真电路包括多个桥接电路，每个桥接电路被配置为通过第一总线与主机设备通信，通过第二总线与多个存储设备的相应存储设备进行通信，并且接收配置为设置桥接器的模式选择信号 电路到主机模式和设备模式之一。 桥电路还被配置为，如果模式选择信号将桥接电路设置为主机模式，则基于仿真选择信号在主模式和从模式之间选择。

公开(公告)号：US20160335542A1

公开(公告)日：2016-11-17

申请号：US14710083

申请日：2015-05-12

申请人： DELL SOFTWARE, INC.

发明人： Shree A. Dandekar ,  Mark W. Davis

IPC分类号： G06N5/02 ,  G06F13/36

CPC分类号： G06F13/36 ,  G06N20/00

摘要： A system, method, and computer-readable medium are disclosed for performing distributed analytics using a metadata encoded decision engine. More specifically, the operation of performing distributed analytics combines metadata encoding of input expectations for models with a multi-tier decision engine. In certain embodiments, the multi-tier decision engine provides arbitrary responses to input failures, including data dropping, routing to additional models, signaling, data conditioning, and even updating of the model parameters themselves. The combination of the processing model, the data input validation, and the decision engine improves the operation of a distributed data processing environment which is focused on predictive and reactive analysis of edge processing data.

摘要翻译： 公开了一种用于使用元数据编码决策引擎进行分布式分析的系统，方法和计算机可读介质。 更具体地，执行分布式分析的操作将对模型的输入期望的元数据编码与多层决策引擎相结合。 在某些实施例中，多层决策引擎提供对输入故障的任意响应，包括丢弃数据，到附加模型的路由，信令，数据调节，甚至更新模型参数本身。 处理模型，数据输入验证和决策引擎的组合改进了分布式数据处理环境的运行，该环境侧重于边缘处理数据的预测和反应分析。

公开(公告)号：US09477501B2

公开(公告)日：2016-10-25

申请号：US14501759

申请日：2014-09-30

申请人： International Business Machines Corporation

发明人： Michael J. Cadigan, Jr. ,  Howard M. Haynie ,  Scot H. Rider ,  Mushfiq U. Saleheen ,  Donald W. Schmidt

IPC分类号： G06F9/455 ,  G06F13/36 ,  G06F9/54 ,  G06F9/50 ,  G06F9/38

CPC分类号： G06F9/455 ,  G06F9/3877 ,  G06F9/45558 ,  G06F9/5077 ,  G06F9/54 ,  G06F13/36

摘要： Embodiments relate to a method for encapsulating a hardware application for virtualization. The method surrounds the hardware application with a service layer controller and ring interfaces. The ring interfaces dictates a virtual function that the hardware application is running. The method controls the hardware application so that the hardware application is reset in between each of a plurality of running jobs. The method tags, by the ring interfaces, each of a plurality of requests with an identifier signifying a virtual function that the respective request belongs to. The method ensures that there are not any outstanding requests following a quiesce of the hardware application.

摘要翻译： 实施例涉及用于封装用于虚拟化的硬件应用程序的方法。 该方法利用服务层控制器和环形接口围绕硬件应用。 环接口指示硬件应用程序正在运行的虚拟功能。 该方法控制硬件应用程序，使硬件应用程序在多个正在运行的作业中的每一个之间复位。 该方法通过环形接口标记具有表示相应请求所属的虚拟功能的标识符的多个请求中的每一个。 该方法确保在硬件应用程序停顿后没有任何未完成的请求。

公开(公告)号：US09471529B2

公开(公告)日：2016-10-18

申请号：US14090149

申请日：2013-11-26

申请人： SK hynix Inc.

发明人： Lian Chun Lee

IPC分类号： G06F13/20 ,  G06F13/42 ,  G06F13/364

CPC分类号： G06F13/1689 ,  G06F13/36 ,  G06F13/364 ,  G06F13/385 ,  G06F13/4068 ,  G06F13/4252

摘要： An embedded storage device for use with a computer device is provided. The embedded storage device includes a microprocessor, a master storage unit, a slave storage unit, and a relay bus. The microprocessor provides a clock signal and creates data transmission link to the computer device. The master storage unit has a master clock pin, at least a master data pin, and a master control pin. The master control pin receives a command signal from the microprocessor. The slave storage unit has a slave clock pin and at least a slave data pin. The relay bus is coupled to the master storage unit and the slave storage unit to enable communication between the master storage unit and the slave storage unit, such that the command signal from the microprocessor is sent from the master storage unit to the slave storage unit via the relay bus.

摘要翻译： 提供了一种用于计算机设备的嵌入式存储设备。 嵌入式存储装置包括微处理器，主存储单元，从存储单元和中继总线。 微处理器提供时钟信号并创建到计算机设备的数据传输链路。 主存储单元具有主时钟引脚，至少一个主数据引脚和一个主控制引脚。 主控制引脚从微处理器接收命令信号。 从存储单元具有从时钟引脚和至少一个从属数据引脚。 中继总线耦合到主存储单元和从存储单元以实现主存储单元和从存储单元之间的通信，使得来自微处理器的命令信号经由主存储单元经由 中继总线。

公开(公告)号：US20160292587A1

公开(公告)日：2016-10-06

申请号：US15035574

申请日：2015-02-27

申请人： RIGETTI & CO., INC.

发明人： Chad Tyler RIGETTI ,  Dane Christoffer THOMPSON

IPC分类号： G06N99/00 ,  G06F15/80

CPC分类号： G06N20/00 ,  G06F13/36 ,  G06F13/4068 ,  G06F15/80 ,  G06N10/00

摘要： In some aspects, a quantum computing system includes an electromagnetic waveguide system. The waveguide system has an interior surface that defines an interior volume of intersecting waveguides. Qubit devices are housed in the waveguide system. In some cases, the intersecting waveguides each define a cutoff frequency, and the qubit devices have qubit operating frequencies below the cutoff frequency. In some cases, coupler devices are housed in the waveguide system; each coupler device is configured to selectively couple a pair of neighboring qubit devices based on control signals received from a control source.

摘要翻译： 在一些方面，量子计算系统包括电磁波导系统。 波导系统具有限定相交波导的内部体积的内表面。 Qubit器件容纳在波导系统中。 在一些情况下，相交的波导每个限定了截止频率，量子位设备的量子位操作频率低于截止频率。 在一些情况下，耦合器装置容纳在波导系统中; 每个耦合器装置被配置为基于从控制源接收的控制信号选择性地耦合一对相邻的量子位装置。

公开(公告)号：US20160283305A1

公开(公告)日：2016-09-29

申请号：US15002460

申请日：2016-01-21

申请人： FUJITSU LIMITED

发明人： Kouji KUGATA

IPC分类号： G06F11/07 ,  G06F13/36 ,  G06F13/40

CPC分类号： G06F13/36 ,  G06F11/0706 ,  G06F11/0754 ,  G06F13/4022

摘要： A PCIe processing unit is connected to a PCI device. A BDF information extracting unit specifies, in response to an occurrence notification of an error, a PCI device in which the error has occurred. An AER address searching unit detects the AER address that is the storage location of error information related to the error held by the PCI device specified by the BDF information extracting unit. An error information acquiring unit collects error information from the AER address that is stored in the PCI device and that is detected by the AER address searching unit. An interrupt determination unit transmits the error information collected by the error information acquiring unit to a core.

摘要翻译： PCIe处理单元连接到PCI设备。 BDF信息提取单元响应于错误的发生通知指定发生错误的PCI设备。 AER地址搜索单元检测作为与由BDF信息提取单元指定的PCI设备保持的错误相关的错误信息的存储位置的AER地址。 错误信息获取单元从存储在PCI设备中并由AER地址搜索单元检测到的AER地址收集错误信息。 中断确定单元将由错误信息获取单元收集的错误信息发送到核心。

公开(公告)号：US20160275038A1

公开(公告)日：2016-09-22

申请号：US14954192

申请日：2015-11-30

申请人： Electronics and Telecommunications Research Institute

发明人： Won Hyuk CHOI ,  Won Young KIM ,  Seung Jo BAE

IPC分类号： G06F13/42 ,  G06F13/40 ,  G06F13/36

CPC分类号： G06F13/4282 ,  G06F13/36 ,  G06F13/4068 ,  Y02D10/14 ,  Y02D10/151

摘要： In a method for communication between hosts using a peripheral component interconnect express (PCIe) dedicated communication module, a PCIe dedicated communication module of a first host generates a first connection buffer for receiving a connection command from a second host, stands by a connection request from the second host, determines whether the first host is connectable to the second host in response to the connection request received from the second host, and, if it is determined that the first host is connectable to the second host, generates a first connection socket connected to the second host for the purpose of data communication. The PCIe dedicated communication module generates a first communication buffer to store data received from the second host, assigns the first communication buffer to the first connection socket, permits the connection between the first and second hosts, and stands by data communication with the second host.

摘要翻译： 在使用外围组件互连快速（PCIe）专用通信模块的主机之间进行通信的方法中，第一主机的PCIe专用通信模块生成用于从第二主机接收连接命令的第一连接缓冲器， 所述第二主机响应于从所述第二主机接收到的所述连接请求，确定所述第一主机是否可连接到所述第二主机，并且如果确定所述第一主机可连接到所述第二主机，则生成连接到所述第二主机的第一连接插座 以数据通信为目的的第二主机。 PCIe专用通信模块生成第一通信缓冲器以存储从第二主机接收的数据，将第一通信缓冲区分配给第一连接套接字，允许第一和第二主机之间的连接，并且通过与第二主机的数据通信来处理。

公开(公告)号：US20160246742A1

公开(公告)日：2016-08-25

申请号：US15051057

申请日：2016-02-23

申请人： NetApp, Inc.

发明人： Jeffrey S. Kimmel

IPC分类号： G06F13/36

CPC分类号： G06F13/36 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/0683

摘要： A hybrid message-based scheduling technique efficiently load balances a storage I/O stack partitioned into one or more non-blocking (i.e., free-running) messaging kernel (MK) threads that execute non-blocking message handlers (i.e., non-blocking services) and one or more operating system kernel blocking threads that execute blocking services. The technique combines the blocking and non-blocking services within a single coherent extended programming environment. The messaging kernel (MK) operates on processors apart from the operating system kernel that are allocated from a predetermined number of logical processors (i.e., hyper-threads) for use by an MK scheduler to schedule the non-blocking services within storage I/O stack as well as allocate a remaining number of logical processors for use by the blocking services. In addition, the technique provides a variation on a synchronization primitive that allows signaling between the two types of services (i.e., non-blocking and blocking) within the extended programming environment.

摘要翻译： 基于混合消息的调度技术有效地将划分成一个或多个非阻塞（即，自由运行）消息传递内核（MK）线程的存储I / O栈负载平衡，执行非阻塞消息处理程序（即，非阻塞 服务）和一个或多个执行阻塞服务的操作系统内核阻塞线程。 该技术将单个连贯扩展编程环境中的阻塞和非阻塞服务相结合。 消息传送内核（MK）对从操作系统内核（从预定数量的逻辑处理器（即，超线程））分配的处理器进行操作，供MK调度程序使用以调度存储I / O内的非阻塞服务 堆栈以及分配剩余数量的逻辑处理器以供阻塞服务使用。 此外，该技术提供允许在扩展编程环境中的两种类型的服务之间的信令（即，非阻塞和阻塞）的同步原语的变体。

公开(公告)号：US20160246612A1

公开(公告)日：2016-08-25

申请号：US14631037

申请日：2015-02-25

申请人： Quanta Computer Inc.

发明人： Maw-Zan Jau ,  Ching-Chih Shih

IPC分类号： G06F9/44 ,  G06F13/36

CPC分类号： G06F9/4416 ,  G06F8/654 ,  G06F13/36

摘要： A computer system can obtain BIOS data from a network storage by a management controller of the computer system. The computer system can emulate a BIOS memory by the management controller based on the BIOS data and initialize the computer system with the BIOS memory emulated by the management controller.

摘要翻译： 计算机系统可以由计算机系统的管理控制器从网络存储器获取BIOS数据。 计算机系统可以由管理控制器基于BIOS数据来模拟BIOS存储器，并且利用由管理控制器模拟的BIOS存储器来初始化计算机系统。

公开(公告)号：US09405566B2

公开(公告)日：2016-08-02

申请号：US13902482

申请日：2013-05-24

申请人： Gaurav Chawla ,  Michael Karl Molloy ,  Robert Wayne Hormuth

发明人： Gaurav Chawla ,  Michael Karl Molloy ,  Robert Wayne Hormuth

IPC分类号： G06F13/36 ,  G06F21/00 ,  G06F9/455

CPC分类号： G06F3/0611 ,  G06F3/0665 ,  G06F3/0685 ,  G06F9/45533 ,  G06F9/45558 ,  G06F13/28 ,  G06F13/36 ,  G06F13/4282 ,  G06F21/00 ,  G06F2009/45579

摘要： Methods and systems for improved access to storage resources include installing a virtual storage appliance as a virtual machine on a hypervisor. The virtual storage appliance installs itself as a virtual PCI-E device and communicates with guest operating systems of the hypervisor using direct memory access via a PCI-E non-transparent bridge. The storage virtual appliance provides access to local and external storage resources with very high performance to applications running under the guest operating system, thereby overcoming performance barriers associated with native hypervisor driver models.

摘要翻译： 用于改进对存储资源的访问的方法和系统包括在虚拟机管理程序上安装虚拟存储设备作为虚拟机。 虚拟存储设备将其本身安装为虚拟PCI-E设备，并通过PCI-E非透明桥接器直接访问内存，与虚拟机管理程序的客户机操作系统进行通信。 存储虚拟设备提供对访问操作系统下运行的应用程序具有非常高性能的本地和外部存储资源的访问，从而克服了与本机管理程序驱动程序模型相关的性能障碍。