公开(公告)号：US08482686B2

公开(公告)日：2013-07-09

申请号：US13762276

申请日：2013-02-07

Applicant: Apple Inc.

Inventor： Cheng Ho Yu ,  Ming Xu ,  Young Bae Park ,  Zhibing Ge ,  Daisuke Nozu ,  Cheng Chen ,  Abbas Jamshidi Roudbari ,  Shih Chang Chang ,  Shawn R. Gettemy

IPC: G02F1/141 ,  G02F1/133 ,  G09G5/00

CPC classification number: G09G3/18 ,  G02F1/13338 ,  G02F2001/134318 ,  G09G3/3648 ,  G09G3/3655 ,  G09G2300/043 ,  G09G2310/0224 ,  G09G2310/0283 ,  G09G2320/0209

Abstract: Display ground plane structures may contain slits. Image pixel electrodes in the display may be arranged in rows and columns. Image pixels in the display may be controlled using gate lines that are associated with the rows and data lines that are associated with the columns. An electric field may be produced by each image pixel electrode that extends through a liquid crystal layer to an associated portion of the ground plane. The slits in the ground plane may have a slit width. Data lines may be located sufficiently below the ground plane and sufficiently out of alignment with the slits to minimize crosstalk from parasitic electric fields. A three-column inversion scheme may be used when driving data line signals into the display, so that pairs of pixels that straddle the slits are each driven with a common polarity. Gate line scanning patterns may be used that enhance display uniformity.

公开(公告)号：US12288522B1

公开(公告)日：2025-04-29

申请号：US18350621

申请日：2023-07-11

Applicant: Apple Inc.

Inventor： Shyuan Yang ,  Salman Kabir ,  Ricardo A Peterson ,  Warren S Rieutort-Louis ,  Ting-Kuo Chang ,  Qing Li ,  Yuchi Che ,  Tsung-Ting Tsai ,  Feng Wen ,  Abbas Jamshidi Roudbari ,  Kyounghwan Kim ,  Graeme M Williams ,  Kingsuk Brahma ,  Yue Jack Chu ,  Junbo Wu ,  Chieh-Wei Chen ,  Bo-Ren Wang ,  Injae Hwang ,  Wenbing Hu

IPC: G09G3/3258

Abstract: An electronic device includes a display and a sensor underneath the display. The display has a full pixel density region and a reduced pixel density region. Compared to pixels in the full pixel density region, pixels in the reduced pixel density region can be controlled using overdriven power supply voltages, overdriven scan control signals, different initialization and reset voltages, and can include capacitors and transistors with different physical and electrical characteristics. Gate drivers provide scan signals to pixels in the full pixel density region, whereas overdrive buffers provide overdrive scan signals to pixels in the reduced pixel density region. The pixels in the full pixel density region and the pixels in the reduced pixel density region can be controlled using different black level or gamma settings for each color channel and can be adjusted physically to match luminance, color, as well as to mitigate differences in temperature and aging impact.

公开(公告)号：US12201004B2

公开(公告)日：2025-01-14

申请号：US17440429

申请日：2020-04-08

Applicant: Apple Inc.

Inventor： Warren S. Rieutort-Louis ,  Woo Shik Jung ,  Abbas Jamshidi Roudbari ,  Shin-Hung Yeh ,  Christopher E. Glazowski ,  Jean-Pierre S. Guillou ,  Yuchi Che

IPC: H10K59/121 ,  H10K59/131 ,  H10K59/35 ,  H10K59/40 ,  H10K59/65

Abstract: An electronic device may include a display and a sensor under the display. The display may include an array of subpixels for displaying an image to a user of the electronic device. At least a portion of the array of subpixels may be selectively removed in a pixel removal region to improve optical transmittance to the sensor through the display. The pixel removal region may include a plurality of pixel free regions that are devoid of thin-film transistor structures, that are devoid of power supply lines, that have continuous open areas due to rerouted row/column lines, that are partially devoid of touch circuitry, that optionally include dummy contacts, and/or have selectively patterned display layers.

公开(公告)号：US11929045B2

公开(公告)日：2024-03-12

申请号：US18167600

申请日：2023-02-10

Applicant: Apple Inc.

Inventor： Shin-Hung Yeh ,  Abbas Jamshidi Roudbari ,  Ting-Kuo Chang

IPC: G09G3/36 ,  G02F1/1362 ,  G09G3/00 ,  H01L27/12

CPC classification number: G09G3/3666 ,  G02F1/136286 ,  G09G3/002 ,  G09G3/3648 ,  H01L27/124 ,  G02F2201/121 ,  G09G2300/0413 ,  G09G2300/0426 ,  G09G2300/0478 ,  G09G2310/0264 ,  G09G2320/0223

Abstract: A display may have an array of pixels such as liquid crystal display pixels. The display may include short pixel rows that span only partially across the display and full-width pixel rows that span the width of the display. The gate lines coupled to the short pixel rows may extend into the inactive area of the display. Supplemental gate line loading structures may be located in the inactive area of the display to increase loading on the gate lines that are coupled to short pixel rows. The supplemental gate line loading structures may include data lines and doped polysilicon that overlap the gate lines in the inactive area. In displays that combine display and touch functionality into a thin-film transistor layer, supplemental loading structures may be used in the inactive area to increase loading on common voltage lines that are coupled to short rows of common voltage pads.

公开(公告)号：US20240065057A1

公开(公告)日：2024-02-22

申请号：US18328427

申请日：2023-06-02

Applicant: Apple Inc.

Inventor： Shin-Hung Yeh ,  Abbas Jamshidi Roudbari ,  Chien-Ya Lee ,  I-Cheng Shih ,  Shyuan Yang ,  Tsung-Ting Tsai

IPC: H10K59/131 ,  H10K59/126 ,  H10K59/121

CPC classification number: H10K59/131 ,  H10K59/126 ,  H10K59/1213

Abstract: A display may include pixels arranged in rows and columns in an active area and display driver circuitry in an inactive area. Data lines for the pixels may be positioned in the active area. Fanout lines may be routed through the active area. Each fanout line may electrically connect the display driver circuitry to a respective data line. One or more pixels may include a drive transistor and a light-emitting diode that are connected in series between a first power supply terminal and a second power supply terminal. A conductive layer may form a first terminal (such as the source terminal, the gate terminal, or the drain terminal) for the drive transistor. A conductive shielding layer may be interposed between the conductive layer and a fanout line to mitigate capacitive coupling between the terminal of the drive transistor and the fanout line.

公开(公告)号：US11852938B2

公开(公告)日：2023-12-26

申请号：US18074393

申请日：2022-12-02

Applicant: Apple Inc.

Inventor： Shin-Hung Yeh ,  Warren S Rieutort-Louis ,  Abbas Jamshidi Roudbari ,  Chien-Ya Lee ,  Lun Tsai

IPC: G02F1/1362 ,  G09G3/20 ,  H10K59/122 ,  H10K59/131

CPC classification number: G02F1/136286 ,  G09G3/20 ,  H10K59/122 ,  H10K59/131 ,  G02F1/13629 ,  G09G2300/0404 ,  G09G2300/0426

Abstract: To minimize the width of a non-light-emitting border region around an opening in the active area, data lines may be stacked in the border region. Data line portions may be formed using three metal layers in three different planes within the border region. A metal layer that forms a positive power signal distribution path in the active area may serve as a data line portion in the border region. A metal layer may be added in the border region to serve as a data line portion in the border region. Data line signals may also be provided to pixels on both sides of an opening in the active area using supplemental data line paths. A supplemental data line path may be routed through the active area of the display to electrically connect data line segments on opposing sides of an opening within the display.

公开(公告)号：US20230389384A1

公开(公告)日：2023-11-30

申请号：US18449611

申请日：2023-08-14

Applicant: Apple Inc.

Inventor： Warren S. Rieutort-Louis ,  Abbas Jamshidi Roudbari ,  Yuchi Che ,  Tsung-Ting Tsai ,  Jiun-Jye Chang ,  Shih Chang Chang ,  Ting-Kuo Chang

IPC: H10K59/131 ,  G09G3/3225 ,  G06F3/041

CPC classification number: H10K59/131 ,  G09G3/3225 ,  G06F3/0412 ,  H10K77/10

Abstract: An electronic device may include a display having display pixels formed in an active area of the display. The display further includes display driver circuitry for driving gate lines that are routed across the display. A hole such as a through hole, optical window, or other inactive region may be formed within the active area of the display. Multiple gate lines carrying the same signal may be merged together prior to being routed around the hole to help minimize the routing line congestion around the border of the hole. Dummy circuits may be coupled to the merged segment portion to help increase the parasitic loading on the merged segments. The hole may have a tapered shape to help maximize the size of the active area. The hole may have an asymmetric shape to accommodate multiple sub-display sensor components.

公开(公告)号：US11823621B2

公开(公告)日：2023-11-21

申请号：US17576619

申请日：2022-01-14

Applicant: Apple Inc.

Inventor： Chin-Wei Lin ,  Shyuan Yang ,  Chuang Qian ,  Abbas Jamshidi Roudbari ,  Ting-Kuo Chang

IPC: G09G3/32 ,  G09G3/3225 ,  G09G3/3233

CPC classification number: G09G3/3225 ,  G09G3/3233 ,  G09G2300/043 ,  G09G2300/0417 ,  G09G2300/0819 ,  G09G2300/0861 ,  G09G2310/0262 ,  G09G2310/0297 ,  G09G2310/06 ,  G09G2310/061 ,  G09G2320/0214 ,  G09G2320/0242 ,  G09G2320/0247 ,  G09G2320/0252 ,  G09G2320/043 ,  G09G2320/045 ,  G09G2320/064 ,  G09G2340/0435

Abstract: A display may have an array of organic light-emitting diode display pixels operating at a low refresh rate. Each display pixel may have six thin-film transistors and one capacitor. One of the six transistors may serve as the drive transistor and may be compensated using the remaining five transistors and the capacitor. One or more on-bias stress operations may be applied before threshold voltage sampling to mitigate first frame dimming. Multiple anode reset and on-bias stress operations may be inserted during vertical blanking periods to reduce flicker and maintain balance and may also be inserted between successive data refreshes to improve first frame performance. Two different emission signals controlling each pixel may be toggled together using a pulse width modulation scheme to help provide darker black levels.

公开(公告)号：US20230197028A1

公开(公告)日：2023-06-22

申请号：US18167600

申请日：2023-02-10

Applicant: Apple Inc.

Inventor： Shin-Hung Yeh ,  Abbas Jamshidi Roudbari ,  Ting-Kuo Chang

IPC: G09G3/36 ,  G09G3/00 ,  H01L27/12 ,  G02F1/1362

CPC classification number: G09G3/3666 ,  G02F1/136286 ,  G09G3/002 ,  G09G3/3648 ,  H01L27/124 ,  G02F2201/121 ,  G09G2300/0413 ,  G09G2300/0426 ,  G09G2300/0478 ,  G09G2310/0264 ,  G09G2320/0223

Abstract: A display may have an array of pixels such as liquid crystal display pixels. The display may include short pixel rows that span only partially across the display and full-width pixel rows that span the width of the display. The gate lines coupled to the short pixel rows may extend into the inactive area of the display. Supplemental gate line loading structures may be located in the inactive area of the display to increase loading on the gate lines that are coupled to short pixel rows. The supplemental gate line loading structures may include data lines and doped polysilicon that overlap the gate lines in the inactive area. In displays that combine display and touch functionality into a thin-film transistor layer, supplemental loading structures may be used in the inactive area to increase loading on common voltage lines that are coupled to short rows of common voltage pads.

公开(公告)号：US11619851B2

公开(公告)日：2023-04-04

申请号：US17525118

申请日：2021-11-12

Applicant: Apple Inc.

Inventor： Shin-Hung Yeh ,  Warren S. Rieutort-Louis ,  Abbas Jamshidi Roudbari ,  Chien-Ya Lee ,  Lun Tsai

IPC: G02F1/1362 ,  G09G3/20 ,  H01L27/32

Abstract: To minimize the width of a non-light-emitting border region around an opening in the active area, data lines may be stacked in the border region. Data line portions may be formed using three metal layers in three different planes within the border region. A metal layer that forms a positive power signal distribution path in the active area may serve as a data line portion in the border region. A metal layer may be added in the border region to serve as a data line portion in the border region. Data line signals may also be provided to pixels on both sides of an opening in the active area using supplemental data line paths. A supplemental data line path may be routed through the active area of the display to electrically connect data line segments on opposing sides of an opening within the display.