公开(公告)号：US20180107759A1

公开(公告)日：2018-04-19

申请号：US15568857

申请日：2015-12-15

Applicant: Sanechips Technology Co., Ltd.

Inventor： Chen Cheng

IPC: G06F17/30

CPC classification number: G06F16/9014 ,  G06F16/00 ,  G06F16/137 ,  G06F16/24532 ,  G06F16/285 ,  G06F16/435

Abstract: A flow classification method and device and a storage medium are provided. The method includes: multiple rules in a rule set are classified to obtain one or more rule subsets according to one or more selected characteristics (101); hash storage is performed according to each classified rule subset (102); and during rule lookup, hash lookup in each parallel hash storage unit is performed according to hash key values of the rules (103).

公开(公告)号：US20180034532A1

公开(公告)日：2018-02-01

申请号：US15551075

申请日：2015-12-29

Applicant: Sanechips Technology Co., Ltd.

Inventor： Gang WU

IPC: H04B7/08 ,  H04L25/03 ,  H04L27/26 ,  H04L25/02

CPC classification number: H04B7/0854 ,  H04B7/08 ,  H04B17/345 ,  H04J11/0036 ,  H04L25/0228 ,  H04L25/0244 ,  H04L25/0246 ,  H04L25/03993 ,  H04L27/26 ,  H04L27/2647

Abstract: Disclosed in an embodiment of the disclosure is an interference rejection combining (IRC) method supporting transmit diversity, in which an N*N interference and noise covariance matrix corresponding to one subcarrier is generated from signals, in a transmit diversity mode, received at cell reference signal (CRS) resource positions via N receiving antennas, where N is greater than or equal to 3; Cholescy decomposition and upper triangular matrix inversion is performed on the N*N interference and noise covariance matrix to obtain an N*N block matrix; the N*N block matrix is expanded to a 2N*2N noise whitening matrix; and the received signals and channel estimation values are whitened according to the noise whitening matrix, and the whitened received signals and channel estimation values used to obtain a minimum mean square error-IRC (MMSE-IRC) processing result. Also disclosed are an IRC device supporting the transmit diversity, and a computer storage medium.

公开(公告)号：US09876424B2

公开(公告)日：2018-01-23

申请号：US15311371

申请日：2014-09-22

Applicant: SANECHIPS TECHNOLOGY CO., LTD.

Inventor： Dong Wei ,  Weisheng Geng

IPC: G05F1/00 ,  H02M3/156 ,  H02M3/04 ,  H02M1/44

CPC classification number: H02M3/156 ,  G05F1/10 ,  G05F1/575 ,  H02M1/44 ,  H02M3/04 ,  H02M2001/0003 ,  H03F1/083 ,  H03F3/45475 ,  H03F2203/45526

Abstract: Disclosed are a compensation network, switching power supply circuit and a circuit compensation method; in the compensation network: an output end of the resistance capacitance network is cascaded to an input end of the unity gain amplifier network, and an output end of the unity gain amplifier network is cascaded to an input end of the error amplifier network; the resistance capacitance network is configured to provide a voltage dividing resistor, and generate a zero and a pole which are mutually canceled; the unity gain amplifier network is configured to generate a zero for canceling a pole in a low pass filter network, and a pole for suppressing a high-frequency noise and improving a phase margin of a switching power supply circuit; and the error amplifier network is configured to generate a pole for increasing low-frequency gain and a zero for canceling another pole in the low pass filter network.

公开(公告)号：US20170329632A1

公开(公告)日：2017-11-16

申请号：US15528145

申请日：2015-04-28

Applicant: Sanechips Technology Co., Ltd.

Inventor： Chao Ma ,  Jinsong Wang ,  Wenqiong Lin

IPC: G06F9/48 ,  G06F9/50

CPC classification number: G06F9/4881 ,  G06F9/5038 ,  G06F2209/5021

Abstract: Disclosed a device scheduling method. A Task Description (TD) in a task queue is read and parsed, to acquire task information of a task corresponding to the TD; and when it is determined that the task has met a starting condition and the task is a task with a highest priority among tasks which currently meet the starting condition, a preset parameter is acquired according to the task information, and the parameter is configured to a device intended to complete the task. A task manager and a storage medium is also disclosed.

公开(公告)号：US09681484B2

公开(公告)日：2017-06-13

申请号：US14655577

申请日：2013-08-29

Applicant: Sanechips Technology Co. Ltd.

Inventor： Zhiwei Mo ,  Ning Chen ,  Xiaoming Zhu

IPC: H04W16/14 ,  H04W76/02 ,  H04W88/02 ,  H04W88/08

CPC classification number: H04W76/15 ,  H04W16/14 ,  H04W88/02 ,  H04W88/08

Abstract: A networking method for mobile terminals is provided, including: dividing a frequency spectrum resource suitable for operation in a mobile communication network into three kinds of frequency bands which are a CB, a LB, and a UB; and establishing, by a calling mobile terminal, a radio communication connection with a called mobile terminal on the CB or the LB or the UB; wherein the calling mobile terminal and the called mobile terminal are implemented by an SDR way. The present disclosure also discloses a mobile terminal. Accordingly, not only a utilization rate of a frequency spectrum resource and a resource usage rate of a base station are improved, a coverage range of the mobile communication network is expanded, but also mobile terminal user experience is improved.

公开(公告)号：US20170140087A1

公开(公告)日：2017-05-18

申请号：US15322420

申请日：2014-11-18

Applicant: Sanechips Technology Co.,Ltd.

Inventor： Qing Zhang ,  Chongxing Gao

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5045 ,  G06F2217/06

Abstract: A method for chip integration is disclosed. The method includes: inputting the parameter file information of a parameter file required to be searched; obtaining a sub-module port list according to the input parameter file information; carrying out the connection between module ports and/or sub-module ports according to the obtained sub-module port list and a pre-configured netlist; and generating a top level file according to the connection between the module ports and/or the sub-module ports, so as to realize the chip integration. A device for chip integration and a storage medium are disclosed as well.

公开(公告)号：US20170077802A1

公开(公告)日：2017-03-16

申请号：US15311371

申请日：2014-09-22

Applicant: SANECHIPS TECHNOLOGY CO., LTD.

Inventor： Dong Wei ,  Weisheng Geng

IPC: H02M3/04 ,  H02M1/44

CPC classification number: H02M3/156 ,  G05F1/10 ,  G05F1/575 ,  H02M1/44 ,  H02M3/04 ,  H02M2001/0003 ,  H03F1/083 ,  H03F3/45475 ,  H03F2203/45526

Abstract: Disclosed are a compensation network, switching power supply circuit and a circuit compensation method; in the compensation network: an output end of the resistance capacitance network is cascaded to an input end of the unity gain amplifier network, and an output end of the unity gain amplifier network is cascaded to an input end of the error amplifier network; the resistance capacitance network is configured to provide a voltage dividing resistor, and generate a zero and a pole which are mutually canceled; the unity gain amplifier network is configured to generate a zero for canceling a pole in a low pass filter network, and a pole for suppressing a high-frequency noise and improving a phase margin of a switching power supply circuit; and the error amplifier network is configured to generate a pole for increasing low-frequency gain and a zero for canceling another pole in the low pass filter network.

Abstract translation: 公开了补偿网络，开关电源电路和电路补偿方法; 在补偿网络中：电阻电容网络的输出端级联到单位增益放大器网络的输入端，单位增益放大器网络的输出端级联到误差放大器网络的输入端; 电阻电容网络被配置为提供分压电阻器，并且生成相互抵消的零和极; 单位增益放大器网络被配置为产生用于消除低通滤波器网络中的极点的零点，以及用于抑制高频噪声并提高开关电源电路的相位裕度的极点; 并且误差放大器网络被配置为产生用于增加低频增益的极点和用于抵消低通滤波器网络中的另一极点的零点。

公开(公告)号：US20160329912A1

公开(公告)日：2016-11-10

申请号：US15108936

申请日：2014-05-20

Applicant: SANECHIPS TECHNOLOGY CO, LTD.

Inventor： Yiyuan Huang

IPC: H03M13/29 ,  G11C29/52 ,  G06F3/06 ,  G06F11/10

CPC classification number: H03M13/2906 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1004 ,  G06F11/1068 ,  G11C29/52 ,  H03M13/098 ,  H03M13/19

Abstract: Provided are a data error correcting method and device, and computer storage medium, the method comprising: respectively setting an index number for each data bit, and generating a first check code according to the index number; and generating a second check code according to the first check code, comparing the first check code with the second check code to determine an erroneous data bit, and correcting the erroneous data bit. The device comprises: a setting module configured to respectively set the index number for each data bit; a first check code generation module configured to generate the first check code according to the index number; a second check code generation module configured to generate the second check code according to the first check code; and a data processing module configured to compare the first check code with the second check code to determine an erroneous data bit, and correct the erroneous data bit.

Abstract translation: 提供了一种数据纠错方法和装置以及计算机存储介质，该方法包括：分别为每个数据位设置索引号，并根据索引号产生第一校验码; 以及根据所述第一校验码生成第二校验码，将所述第一校验码与所述第二校验码进行比较，以确定错误数据位，以及校正所述错误数据位。 该设备包括：设置模块，被配置为分别为每个数据比特设置索引号; 第一校验码生成模块，被配置为根据所述索引号生成所述第一校验码; 第二检验码生成模块，被配置为根据第一检验码生成第二检验码; 以及数据处理模块，被配置为将所述第一校验码与所述第二校验码进行比较，以确定错误的数据位，并校正所述错误数据位。

公开(公告)号：US20250156094A1

公开(公告)日：2025-05-15

申请号：US19021785

申请日：2025-01-15

Applicant: SANECHIPS TECHNOLOGY CO., LTD.

Inventor： Yingjie HU ,  Jinfeng Shi ,  Rongrong Shen ,  Yunlong Shi

IPC: G06F3/06

Abstract: Disclosed are a storage scheduling method, a storage scheduling apparatus, a storage scheduling device and a computer-readable storage medium. The method includes: obtaining a current first amount of space used of an on-chip memory, and obtaining a current write bandwidth of an off-chip memory; determining a second queue from each first queue stored in the on-chip memory in response to that the first amount of space used is greater than a preset first threshold value and the write bandwidth is less than a preset second threshold value; the queue congestion degree is evaluated according to a preset congestion degree evaluation index; setting a storage state of the second queue to an off-chip state; and storing a target message in a memory indicated by a storage state of a queue where the target message is located.

公开(公告)号：US12200248B2

公开(公告)日：2025-01-14

申请号：US18010356

申请日：2021-06-01

Applicant: SANECHIPS TECHNOLOGY CO., LTD.

Inventor： Wei Yang ,  Ke Xu ,  Dehui Kong ,  Jianjun Song ,  Fang Zhu

IPC: H04N19/59 ,  G06T5/50 ,  G06T7/11 ,  H04N19/51

Abstract: The present application provides a video processing method, a device, and a storage medium. The method includes: coding and decoding an original video to obtain a mixed resolution video, where the mixed resolution video includes a first resolution frame and a second resolution frame each corresponding to a key frame, and a third resolution frame corresponding to a non-key frame, where the first resolution frame has a resolution higher than a resolution of the second resolution frame or a resolution of the third resolution frame; and amplifying, according to the first resolution frame and the second resolution frame, the third resolution frame corresponding to the non-key frame to output an amplified video, where the amplified video includes the first resolution frame corresponding to the key frame, and an amplified target frame corresponding to the non-key frame.