公开(公告)号：US20190034097A1

公开(公告)日：2019-01-31

申请号：US15723014

申请日：2017-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng

IPC: G06F3/06

CPC classification number: G06F3/0617 ,  G06F3/0653 ,  G06F3/0659 ,  G06F12/0292 ,  G06F13/16 ,  G06F15/7821 ,  G06F2212/1016

Abstract: A method of coordinating memory commands in a high-bandwidth memory HBM+ system, the method including sending a host memory controller command from a host memory controller to a memory, receiving the host memory controller command at a coordinating memory controller, forwarding the host memory controller command from the coordinating memory controller to the memory, and scheduling, by the coordinating memory controller, a coordinating memory controller command based on the host memory controller command.

公开(公告)号：US10180906B2

公开(公告)日：2019-01-15

申请号：US15272339

申请日：2016-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tyler Stocksdale ,  Mu-Tien Chang ,  Hongzhong Zheng

IPC: G06F12/0862 ,  G06F12/0893

Abstract: A system and method for using high bandwidth memory as cache memory. A high bandwidth memory may include a logic die, and, stacked on the logic die, a plurality of dynamic read-only memory dies. The logic die may include a cache manager, that may interface to external systems through an external interface conforming to the JESD235A standard, and that may include an address translator, a command translator, and a tag comparator. The address translator may translate each physical address received through the external interface into a tag value, a tag address in the stack of memory dies, and a data address in the stack of memory dies. The tag comparator may determine whether a cache hit or cache miss has occurred, according to whether the tag value generated by the address translator matches the tag value stored at the tag address.

公开(公告)号：US20180293175A1

公开(公告)日：2018-10-11

申请号：US15662072

申请日：2017-07-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien Chang ,  Heehyun Nam ,  Youngsik Kim ,  Youngjin Cho ,  Dimin Niu ,  Hongzhong Zheng

IPC: G06F12/121

Abstract: A method of choosing a cache line of a plurality of cache lines of data for eviction from a frontend memory, the method including assigning a baseline replacement score to each way of a plurality of ways of a cache, the ways respectively storing the cache lines, assigning a validity score to each way based on a degree of validity of the cache line stored in each way, assigning an eviction decision score to each way based on a function of the baseline replacement score for the way and the validity score for the way, and choosing a cache line of the way having a highest eviction decision score as the cache line for eviction.

公开(公告)号：US20180181495A1

公开(公告)日：2018-06-28

申请号：US15905746

申请日：2018-02-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Frederic Sala ,  Chaohong Hu ,  Hongzhong Zheng ,  Dimin Niu ,  Mu-Tien Chang

IPC: G06F12/1018 ,  G11C29/00 ,  G06F12/0802

CPC classification number: G06F12/1018 ,  G06F3/0619 ,  G06F3/0641 ,  G06F3/065 ,  G06F3/0685 ,  G06F12/0802 ,  G11C29/74

Abstract: A method of memory deduplication includes identifying hash tables each corresponding to a hash function, and each including physical buckets, each physical bucket including ways and being configured to store data, identifying virtual buckets each including some physical buckets, and each sharing a physical bucket with another virtual bucket, identifying each of the physical buckets having data stored thereon as being assigned to a single virtual bucket, hashing a data line according to a hash function to produce a hash value, determining whether a corresponding virtual bucket has available space for a block of data according to the hash value, sequentially moving data from the corresponding virtual bucket to an adjacent virtual bucket when the corresponding virtual bucket does not have available space until the corresponding virtual bucket has space for the block of data, and storing the block of data in the corresponding virtual bucket.

公开(公告)号：US09761296B2

公开(公告)日：2017-09-12

申请号：US15299445

申请日：2016-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien Chang ,  Krishna Malladi ,  Dimin Niu ,  Hongzhong Zheng

IPC: G11C5/14 ,  G11C11/406 ,  G11C11/4076 ,  G11C5/04 ,  G06F13/16

CPC classification number: G11C11/40615 ,  G06F13/1636 ,  G11C5/04 ,  G11C11/40618 ,  G11C11/4076

Abstract: A memory (1205) is disclosed. The memory (1205) can includes a stack of dynamic Random Access Memory (DRAM) cores (1210, 1215, 1220, 1225) in a three-dimensional stacked memory architecture (1230). Each of the DRAM cores (1210, 1215, 1220, 1225) can include a plurality of banks (205-1, 205-2, 205-3, 205-4) to store data. The memory (1205) can also include logic layer (1235) which can include an interface (1305) to connect the memory (1205) with a processor (120). The logic layer (1235) can also include a refresh engine (115) that can be used to refresh one of the plurality of banks (205-1, 205-2, 205-3, 205-4) and a Smart Refresh Component (305) that can advise the refresh engine (115) which bank to refresh using an out-of-order per-bank refresh. The Smart Refresh Component (305) can use a logic (415) to identify a farthest bank in the pending transactions in the transaction queue (430) at the time of refresh.