OPTIMIZATION FOR ARTIFICIAL NEURAL NETWORK MODEL AND NEURAL PROCESSING UNIT

    公开(公告)号:US20230090720A1

    公开(公告)日:2023-03-23

    申请号:US17989761

    申请日:2022-11-18

    Inventor: Lok Won KIM

    Abstract: A computer-implemented apparatus installed and executed in a computer to search an optimal design of a neural processing unit (NPU), a hardware accelerator used for driving a computer-implemented artificial neural network (ANN) is disclosed. The NPU comprises a plurality of blocks connected in a form of pipeline, and the number of the plurality blocks and the number of the layers within each block of the plurality blocks are in need of optimization to reduce hardware resources demand and electricity power consumption of the ANN while maintaining the inference accuracy of the ANN at an acceptable level. The computer-implemented apparatus searches for and then outputs an optimal L value and an optimal C value when a first set of candidate values for a number of layers L and a second set of candidate values for a number of channels C per each layer of the ANN is provided.

    NPU IMPLEMENTED FOR ARTIFICIAL NEURAL NETWORKS TO PROCESS FUSION OF HETEROGENEOUS DATA RECEIVED FROM HETEROGENEOUS SENSORS

    公开(公告)号:US20230045552A1

    公开(公告)日:2023-02-09

    申请号:US17972375

    申请日:2022-10-24

    Inventor: Lok Won KIM

    Abstract: A neural processing unit (NPU) includes a controller including a scheduler, the controller configured to receive from a compiler a machine code of an artificial neural network (ANN) including a fusion ANN, the machine code including data locality information of the fusion ANN, and receive heterogeneous sensor data from a plurality of sensors corresponding to the fusion ANN; at least one processing element configured to perform fusion operations of the fusion ANN including a convolution operation and at least one special function operation; a special function unit (SFU) configured to perform a special function operation of the fusion ANN; and an on-chip memory configured to store operation data of the fusion ANN, wherein the schedular is configured to control the at least one processing element and the on-chip memory such that all operations of the fusion ANN are processed in a predetermined sequence according to the data locality information.

    NPU, EDGE DEVICE AND OPERATION METHOD THEREOF

    公开(公告)号:US20220318606A1

    公开(公告)日:2022-10-06

    申请号:US17502008

    申请日:2021-10-14

    Inventor: Lok Won KIM

    Abstract: A neural processing unit (NPU) includes an internal memory storing information on combinations of a plurality of artificial neural network (ANN) models, the plurality of ANN models including first and second ANN models; a plurality of processing elements (PEs) to process first operations and second operations of the plurality of ANN models in sequence or in parallel, the plurality of PEs including first and second groups of PEs; and a scheduler to allocate to the first group of PEs a part of the first operations for the first ANN model and to allocate to the second group of PEs a part of the second operations for the second ANN model, based on an instruction related to information on an operation sequence of the plurality of ANN models or further based on ANN data locality information. The first and second operations may be performed in parallel or in a time division.

    METHOD FOR ARTIFICIAL NEURAL NETWORK AND NEURAL PROCESSING UNIT

    公开(公告)号:US20220207337A1

    公开(公告)日:2022-06-30

    申请号:US17560270

    申请日:2021-12-23

    Inventor: Lok Won KIM

    Abstract: A method performs a plurality of operations on an artificial neural network (ANN). The plurality of operations includes storing in at least one memory a set of weights, at least a portion of a first batch channel of a plurality of batch channels, and at least a portion of a second batch channel of the plurality of batch channels; and calculating the at least a portion of the first batch channel and the at least a portion of the second batch channel by the set of weights. A batch mode, configured to process a plurality of input channels, can determine the operation sequence in which the on-chip memory and/or internal memory stores and computes the parameters of the ANN. Even if the number of input channels increases, processing may be performed with one neural processing unit including a memory configured in consideration of a plurality of input channels.

    METHOD AND SYSTEM FOR BIT QUANTIZATION OF ARTIFICIAL NEURAL NETWORK

    公开(公告)号:US20220138529A1

    公开(公告)日:2022-05-05

    申请号:US17547158

    申请日:2021-12-09

    Inventor: Lok Won KIM

    Abstract: The present disclosure provides a method for bit quantization of an artificial neural network. This method may comprise: (a) a step of selecting one parameter or one parameter group to be quantized in an artificial neural network; (b) a bit quantization step of reducing the size of data representation for the selected parameter or parameter group to bits; (c) a step of determining whether the accuracy of the artificial neural network is greater than or equal to a predetermined target value; and (d) a step of, when the accuracy of the artificial neural network is greater than or equal to the target value, repeatedly performing said step (a) to step (c).

    MEMORY CONTROLLER, PROCESSOR AND SYSTEM FOR ARTIFICIAL NEURAL NETWORK

    公开(公告)号:US20220137868A1

    公开(公告)日:2022-05-05

    申请号:US17513913

    申请日:2021-10-29

    Inventor: Lok Won KIM

    Abstract: A system for an artificial neural network (ANN) includes a processor configured to output a memory control signal including an ANN data locality; a main memory in which data of an ANN model corresponding to the ANN data locality is stored; and a memory controller configured to receive the memory control signal from the processor and to control the main memory based on the memory control signal. The memory controller may be further configured to control, based on the memory control signal, a read or write operation of data of the main memory required for operation of the artificial neural network. Thus, the system optimizes an ANN operation of the processor by utilizing the ANN data locality of the ANN model, which operates at a processor-memory level.

    METHOD AND SYSTEM FOR BIT QUANTIZATION OF ARTIFICIAL NEURAL NETWORK

    公开(公告)号:US20210264232A1

    公开(公告)日:2021-08-26

    申请号:US17254039

    申请日:2020-02-21

    Inventor: Lok Won KIM

    Abstract: The present disclosure provides a method for bit quantization of an artificial neural network. This method may comprise: (a) a step of selecting one parameter or one parameter group to be quantized in an artificial neural network; (b) a bit quantization step of reducing the size of data representation for the selected parameter or parameter group to bits; (c) a step of determining whether the accuracy of the artificial neural network is greater than or equal to a predetermined target value; and (d) a step of, when the accuracy of the artificial neural network is greater than or equal to the target value, repeatedly performing said step (a) to step (c).

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