METHOD AND DEVICE FOR DETECTING DEFICIENCY OF EXTERNAL COMPENSATION LINE, AND DISPLAY MODULE

    公开(公告)号:US20190108777A1

    公开(公告)日:2019-04-11

    申请号:US15988446

    申请日:2018-05-24

    Inventor: Can YUAN

    Abstract: The present disclosure provides a method and a device for detecting an external compensation line and a display module. The method includes steps of: within a resetting time period of each detection stage, applying a resetting voltage to the external compensation line and entering a detection time period after a resetting duration; and within the detection time period of each detection stage, controlling the external compensation line to be in a floating state, applying a data voltage to a data line, applying a power source voltage to a power source voltage input end, applying a data write-in control voltage to a data write-in control end, applying an external compensation control voltage to an external compensation control end, detecting a voltage across the external compensation line after a detection duration, and determining whether or not there is a short circuit for the external compensation line in accordance with the voltage across the external compensation line.

    BRIGHTNESS COMPENSATION METHOD FOR DISPLAY APPARATUS, AND DISPLAY APPARATUS

    公开(公告)号:US20190066601A1

    公开(公告)日:2019-02-28

    申请号:US15989746

    申请日:2018-05-25

    Abstract: A brightness compensation method for a display apparatus, and a display apparatus are disclosed. The brightness compensation method includes: for each row of display units, turning on the row S times during a display time of one frame; inputting, to each display unit in the row a pixel data signal of the frame corresponding to the display unit, when the row is turned on for the i-th time; inputting, to a to-be-compensated display unit in the row, a compensation signal, and controlling other display unit than the to-be-compensated display unit in the row to present black, when the row is turned on for each time other than the i-th time; wherein both S and i are integers, S≥2, 1≤i≤S; for every two adjacent rows of display units, a time interval of same turning-ons of the latter and the former is the same.

    ARRAY SUBSTRATE AND METHOD OF FABRICATING THE SAME

    公开(公告)号:US20190058026A1

    公开(公告)日:2019-02-21

    申请号:US15765178

    申请日:2017-07-07

    Abstract: The present application provides an array substrate, which includes a base substrate, and a first electrode, a first protection layer, a semiconductor electrode, a second protection layer and a second electrode formed sequentially on the base substrate. The second electrode and the semiconductor electrode constitute a storage capacitor, and the first electrode is below the semiconductor electrode to make the semiconductor electrode conductive. In a direction perpendicular to the base substrate, the thickness of at least a portion of the first protection layer in the first electrode area is less than that of other portions of the first protection layer outside the first electrode area, the first electrode area being an area defined by the projection of the first electrode on the first protection layer.

    PIXEL CIRCUIT AND DRIVING METHOD THEREOF, AND DISPLAY DEVICE

    公开(公告)号:US20250061851A1

    公开(公告)日:2025-02-20

    申请号:US18554822

    申请日:2023-01-12

    Abstract: A pixel circuit and a driving method thereof, and a display device are disclosed. The pixel circuit includes a driving circuit, a data writing circuit, a reset circuit, a light-emitting control circuit and a light-emitting element. The driving circuit includes a control terminal, a first terminal and a second terminal; the data writing circuit is connected to a first node to apply a data voltage; the reset circuit is connected to the first node to apply a reference voltage. The pixel circuit further includes a partition control circuit, which is connected to the first node and the control terminal, and is configured to apply the data voltage and the reference voltage to the control terminal; the reset circuit is connected to one of the first terminal and the second terminal of the driving circuit, and the reset circuit is further configured to apply an initialization voltage to the driving circuit.

    DISPLAY SUBSTRATE
    77.
    发明申请

    公开(公告)号:US20250037662A1

    公开(公告)日:2025-01-30

    申请号:US18918667

    申请日:2024-10-17

    Abstract: A display substrate and a display panel are provided. The display substrate includes: a base substrate; and a plurality of sub-pixels. Each sub-pixel includes a light-emitting element and a pixel circuit; the pixel circuit includes a driving circuit, a data writing circuit, a first control circuit, a second control circuit, and a light-emitting control circuit; the driving circuit is configured to control the driving current flowing through the light-emitting element; the light-emitting control circuit is configured to apply the driving current to the light-emitting element; the first control circuit is configured to write a reference voltage into the driving circuit; the second control circuit is configured to write an initial voltage into the first electrode of the light-emitting element; and orthographic projections of at least part of pixel circuits of every two adjacent sub-pixels in a same row of sub-pixels on the base substrate are mirror-symmetrical.

    DISPLAY PANEL AND DISPLAY DEVICE
    80.
    发明公开

    公开(公告)号:US20240169925A1

    公开(公告)日:2024-05-23

    申请号:US17779164

    申请日:2021-03-29

    Abstract: A display panel includes sub-pixels and a scan driving circuit. The scan driving circuit includes a plurality of stages of shift registers including at least one first shift register and at least one second shift register, and a plurality of clock signal lines including at least one first sub-clock signal line and at least one second sub-clock signal line. Each shift register includes a first sub-circuit and a second sub-circuit. A first sub-clock signal line in the at least one first sub-clock signal line is electrically connected to a first sub-circuit in a first shift register in the at least one first shift register. A second sub-clock signal line in the at least one second sub-clock signal line is electrically connected to one sub-circuit of a first sub-circuit and a second sub-circuit in a second shift register in the at least one second shift register.

Patent Agency Ranking