公开(公告)号：US10665319B1

公开(公告)日：2020-05-26

申请号：US16137187

申请日：2018-09-20

Applicant: Amazon Technologies, Inc.

Inventor： Alex Levin ,  Ron Diamant ,  Georgy Zorik Machulsky

IPC: G11C29/42 ,  G06F11/10 ,  G11C29/52

Abstract: Approaches for testing memory devices, such as DRAMs, are described that can quickly identify various potential storage issues. The memory space for a device can be divided into subspaces that can be tested concurrently. A starting address is determined for each memory sub-space, and addresses are identified that are within a Hamming distance of the starting address, where a single Hamming distance or multiple Hamming distances can be used. Once a list of addresses is generated, a test pattern can be written to, and read from, the corresponding addresses. Differences from the expected pattern can be indicative of problems with the memory device, whether before user deployment or while storing live data. If there are specific problems suspected, targeted testing can be utilized that does not test the entirety of the memory space.

公开(公告)号：US10594476B1

公开(公告)日：2020-03-17

申请号：US15966127

申请日：2018-04-30

Applicant: AMAZON TECHNOLOGIES, INC.

Inventor： Ron Diamant ,  Nafea Bshara ,  Erez Izenberg

IPC: H04L9/06 ,  H04L9/08

Abstract: A hardware cipher module to cipher a packet. The cipher module includes a key scheduling engine and a ciphering engine. The key scheduling engine is configured to receive a compact key and iteratively generate a set of round keys, including a first round key, based on the compact key and determine, based upon a cipher mode indication and a type of ciphering whether to generate a key-scheduling-done indication after the first round key is generated and before all of the set of round keys are generated or to generate the key-scheduling-done indication after all of the set of round keys is generated. The ciphering engine is configured to begin to cipher the packet with one of the set of round keys as a result of receiving the key schedule done indication.

公开(公告)号：US10565382B1

公开(公告)日：2020-02-18

申请号：US15389152

申请日：2016-12-22

Applicant: Amazon Technologies, Inc.

Inventor： Ron Diamant ,  Alex Levin ,  Ihab Bishara

IPC: H04L29/06 ,  G06F21/57 ,  G06F9/4401 ,  H04L9/08

Abstract: Methods and apparatus are disclosed for securing executable code for execution with a processor using a trusted platform module (TPM). In one example of the disclosed technology, a method of decrypting executable code for execution includes measuring values stored in a CPU boot ROM and measuring second values for executable code stored in non-volatile memory, storing the resulting measurement value in a TPM platform configuration register. The PCR value is used to unseal a key stored in non-volatile memory of the TPM, which key is used to decrypt executable code for execution. Security can be further enhanced by destroying the values stored in the PCR by performing additional measurement operations with the TPM PCR used to generate the measurement value.

公开(公告)号：US10432216B1

公开(公告)日：2019-10-01

申请号：US15614161

申请日：2017-06-05

Applicant: AMAZON TECHNOLOGIES, INC.

Inventor： Ron Diamant ,  Svetlana Kantorovych ,  Ori Weber ,  Michael Baranchik

IPC: H03M7/30 ,  H03K19/173 ,  G06F16/25

Abstract: A compression circuit includes a buffer, a selection circuit, a compare circuit, and a control circuit. The buffer stores uncompressed data. The selection circuit generates a read pointer value to the buffer. The control circuit contains a programmable configuration register. The configuration register stores a depth value for reading uncompressed data from the history buffer. The control circuit generates control signals to the selection circuit to cause the selection circuit to iteratively increment the read pointer value from an initial value to a second value that corresponds to the depth value. Responsive to the second value corresponding to the depth value, the control circuit resets the read pointer value to the initial value. The compare circuit compares input symbols from a data source to uncompressed data from the buffer history to thereby generate output compressed data.

公开(公告)号：US10284226B1

公开(公告)日：2019-05-07

申请号：US16029805

申请日：2018-07-09

Applicant: AMAZON TECHNOLOGIES, INC.

Inventor： Ron Diamant ,  Michael Baranchik ,  Ori Weber

IPC: H03M7/40 ,  H03M7/30

Abstract: A computing system includes a network interface, a processor, and a decompression circuit. In response to a compression request from the processor the decompression circuit compresses data to produce compressed data and transmits the compressed data through the network interface. In response to a decompression request from the processor for compressed data the decompression circuit retrieves the requested compressed data, speculatively detects codewords in each of a plurality of overlapping bit windows within the compressed data, selects valid codewords from some, but not all of the overlapping bit windows, decodes the selected valid codewords to generate decompressed data, and provides the decompressed data to the processor.

公开(公告)号：US10218382B2

公开(公告)日：2019-02-26

申请号：US15976312

申请日：2018-05-10

Applicant: Amazon Technologies, Inc.

Inventor： Ori Weber ,  Ron Diamant ,  Yair Sandberg

IPC: H03M7/34 ,  H03M7/30 ,  G06T9/00 ,  G06T3/40

Abstract: The following description is directed to decompression using cascaded history buffers. In one example, an apparatus can include a decompression pipeline configured to decompress compressed data comprising code words that reference a history of decompressed data generated from the compressed data. The apparatus can include a first-level history buffer configured to store a more recent history of the decompressed data received from the decompression pipeline. The apparatus can include a second-level history buffer configured to store a less recent history of the decompressed data received from the first-level history buffer.

公开(公告)号：US10134464B1

公开(公告)日：2018-11-20

申请号：US15468704

申请日：2017-03-24

Applicant: Amazon Technologies, Inc.

Inventor： Ron Diamant ,  Jonathan Cohen ,  Elad Valfer

IPC: G11C8/00 ,  G11C11/408 ,  G11C13/00

Abstract: A decoder is disclosed that is used to select an area of address space in an Integrated Circuit. The decoder uses a hardware shifting module that performs shift operations on constants. Such a structure reduces an overall area consumption of the shifting module. Additionally, the decoder can perform a multi-bit shift operation in a single clock cycle.

公开(公告)号：US10102072B2

公开(公告)日：2018-10-16

申请号：US15282254

申请日：2016-09-30

Applicant: Amazon Technologies, Inc.

Inventor： Ron Diamant ,  Nafea Bshara ,  Yaniv Shapira ,  Guy Nakibly

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/20

Abstract: A method for calculating a plurality (M) of redundancy blocks for multiple (N) data blocks of a plurality (D) of words each, the method comprises: receiving the number (M) of redundancy blocks by a calculator that comprises multiple (R) calculation units; configuring the calculator according to M and R; concurrently calculating, if M equals R, by the multiple (R) calculation units of the calculator, R sets of parity vectors, each set includes a plurality (D) of parity vectors; and calculating the plurality (M) of the redundancy blocks based on the R sets of parity vectors.

公开(公告)号：US09607682B1

公开(公告)日：2017-03-28

申请号：US15083077

申请日：2016-03-28

Applicant: Amazon Technologies, Inc.

Inventor： Ron Diamant ,  Jonathan Cohen ,  Elad Valfer

IPC: G11C8/00 ,  G11C11/408 ,  G11C7/10 ,  G11C8/12 ,  G11C8/10

CPC classification number: G11C11/4087 ,  G06F12/06 ,  G06F2212/1041 ,  G11C7/1006 ,  G11C8/10 ,  G11C8/12

Abstract: A decoder is disclosed that is used to select an area of address space in an Integrated Circuit. The decoder uses a hardware shifting module that performs shift operations on constants. Such a structure reduces an overall area consumption of the shifting module. Additionally, the decoder can perform a multi-bit shift operation in a single clock cycle.

公开(公告)号：US12271732B1

公开(公告)日：2025-04-08

申请号：US17937333

申请日：2022-09-30

Applicant: Amazon Technologies, Inc.

Inventor： Paul Gilbert Meyer ,  Ron Diamant ,  Sundeep Amirineni

IPC: G06F9/22 ,  G06F9/30 ,  G06F9/38 ,  G06F15/78

Abstract: A technique to program a compute channel having multiple computational circuit blocks coupled in series in a pipeline can include receiving a machine instruction for the compute channel. The machine instruction is decoded to obtain an opcode, and the opcode can be used as an index to access an opcode entry in an opcode table. The opcode entry contains a pointer to a microoperation, and the pointer can be used to access a microoperation represented by a control entry in a control table and a datapath configuration entry in a datapath table. The microoperation can then be issued to the compute channel by configuring the compute channel with the control entry and the datapath configuration entry.