公开(公告)号：US06291295B1

公开(公告)日：2001-09-18

申请号：US09316979

申请日：1999-05-24

申请人： Kuo-Tai Huang ,  Tri-Rung Yew ,  Water Lur

发明人： Kuo-Tai Huang ,  Tri-Rung Yew ,  Water Lur

IPC分类号： H01L218242

CPC分类号： H01L28/60 ,  H01L21/02129 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02332 ,  H01L21/3105 ,  H01L21/31625 ,  H01L21/76895 ,  H01L27/10852 ,  H01L28/84

摘要： A method of fabricating a capacitor. An isolation layer is formed on a substrate. An ion implantation step is performed. The isolation layer is patterned to form an opening in the isolation layer. The opening exposes a portion of the substrate. A patterned conductive layer is formed on the isolation layer to fill the opening. A hemispherical grained silicon layer is performed on the conductive layer. In addition, the step order of the ion implantation step can be changed. The ion implantation can also be performed after the opening is formed.

摘要翻译： 一种制造电容器的方法。 在基板上形成隔离层。 执行离子注入步骤。 隔离层被图案化以在隔离层中形成开口。 开口露出基底的一部分。 在隔离层上形成图案化的导电层以填充开口。 在导电层上进行半球状的硅层。 此外，可以改变离子注入步骤的步骤顺序。 离子注入也可以在开口形成之后进行。

公开(公告)号：US06281143B1

公开(公告)日：2001-08-28

申请号：US09334864

申请日：1999-06-17

申请人： Michael W C Huang ,  Hsueh-Hao Shih ,  Gwo-Shii Yang ,  Tri-Rung Yew

发明人： Michael W C Huang ,  Hsueh-Hao Shih ,  Gwo-Shii Yang ,  Tri-Rung Yew

IPC分类号： H01L2131

CPC分类号： H01L21/76897 ,  H01L21/28518 ,  H01L21/3143 ,  H01L21/321

摘要： A method for forming borderless contact is disclosed. The method includes providing a substrate with active areas and a trench isolation region in which the active areas are silcide. Then, the substrate is nitridized such that a titanium nitride layer is formed on the active areas and a silicon oxynitride is formed on the trench isolation region. A dielectric layer is deposited on the substrate and an opening is etched in the dielectric layer in which the opening overlies both a portion of the trench isolation region and a portion of the active area.

摘要翻译： 公开了一种形成无边界接触的方法。 该方法包括提供具有有源区的衬底和沟槽隔离区，其中有源区是硅化物。 然后，将衬底氮化，使得在有源区上形成氮化钛层，并在沟槽隔离区上形成氮氧化硅。 介电层沉积在衬底上，并且在电介质层中蚀刻开口，其中开口覆盖沟槽隔离区的一部分和有源区的一部分。

公开(公告)号：US06235606B1

公开(公告)日：2001-05-22

申请号：US09225031

申请日：1999-01-04

申请人： Michael W C Huang ,  Kuo-Tai Huang ,  Hsiao-Ling Lu ,  Tri-Rung Yew

发明人： Michael W C Huang ,  Kuo-Tai Huang ,  Hsiao-Ling Lu ,  Tri-Rung Yew

IPC分类号： H01L2176

CPC分类号： H01L21/76897 ,  H01L21/76224

摘要： A method for fabricating a shallow trench isolation. A pad oxide layer and a mask layer are formed over a substrate. The pad oxide layer, the mask layer, and the substrate are patterned to form a trench exposing a portion of the substrate. A liner oxide layer is formed on the substrate exposed by the trench. An isolation layer is formed over the substrate to cover the liner oxide layer. The isolation layer is conformal to the trench. An oxide layer is formed over the substrate to fill the trench. A portion of the oxide layer and the isolation layer is removed until the mask layer is exposed. The mask layer and the pad oxide layer are removed to form a shallow trench isolation.

摘要翻译： 一种制造浅沟槽隔离的方法。 在衬底上形成衬垫氧化物层和掩模层。 将衬垫氧化物层，掩模层和衬底图案化以形成暴露衬底的一部分的沟槽。 在由沟槽暴露的衬底上形成衬里氧化物层。 在衬底上形成隔离层以覆盖衬里氧化物层。 隔离层与沟槽保形。 在衬底上形成氧化物层以填充沟槽。 除去氧化物层和隔离层的一部分直到掩模层露出。 去除掩模层和焊盘氧化物层以形成浅沟槽隔离。

公开(公告)号：US06184142B2

公开(公告)日：2001-02-06

申请号：US09302204

申请日：1999-04-26

申请人： Hsien-Ta Chung ,  Chan-Lon Yang ,  Tong-Yu Chen ,  Tri-Rung Yew

发明人： Hsien-Ta Chung ,  Chan-Lon Yang ,  Tong-Yu Chen ,  Tri-Rung Yew

IPC分类号： H01L2100

CPC分类号： H01L21/76807 ,  H01L21/31144 ,  H01L21/76802

摘要： A simplified method is disclosed for etching low k organic dielectric film. A substrate is provided with a hardmask layer and low k organic dielectric layer formed thereon in which hardmask layer is on the dielectric layer. A layer of photoresist is formed on the hardmask layer and imaged with a pattern by exposure through a dark field mask. As a key step, the pattern is transferred into the hardmask layer by dry etching and then the photoresist is stripped in-situ. Then, the interconnect is formed by using dry etching the low k organic dielectric layer using the hardmask layer as a mask, and readying it for the next semiconductor process.

摘要翻译： 公开了一种用于蚀刻低k有机介电膜的简化方法。 衬底上设置有硬掩模层和形成在其上的低k有机介电层，其中硬掩模层位于电介质层上。 在硬掩模层上形成光致抗蚀剂层，并通过暗场掩模曝光以图案成像。 作为关键步骤，通过干蚀刻将图案转移到硬掩模层中，然后原位剥离光致抗蚀剂。 然后，通过使用硬掩模层作为掩模使用干式蚀刻低k有机介电层形成互连，并将其准备用于下一个半导体工艺。

公开(公告)号：US6159661A

公开(公告)日：2000-12-12

申请号：US73997

申请日：1998-05-07

申请人： Yimin Huang ,  Tri-Rung Yew

发明人： Yimin Huang ,  Tri-Rung Yew

IPC分类号： H01L21/314 ,  H01L21/768 ,  G03F7/00

CPC分类号： H01L21/76832 ,  H01L21/3143 ,  H01L21/7681

摘要： An improved dual damascene process for forming metal interconnects comprising the steps of providing a semiconductor substrate that has a conductive layer, a first dielectric layer and a first mask layer already formed thereon. The first dielectric layer is made from a low-k dielectric material. A first silicon oxynitride (SiON) layer is formed over the first mask layer. Next, the first silicon oxynitride layer is patterned, and then the first mask layer is etched using the first silicon oxynitride as a mask. Subsequently, a second dielectric layer and a second mask layer are formed over the first silicon oxynitride. The second dielectric layer can be made from a low-k dielectric material. Next, a second silicon oxynitride layer is formed over the second mask layer. Thereafter, the second silicon oxynitride layer is patterned, and then the second mask layer is etched using the second silicon oxynitride layer as a mask. Subsequently, using the second mask layer as a mask, the second dielectric layer is etched to form a metal wire opening. Etching continues down the metal wire opening to form a via opening in the first dielectric layer that exposes the conductive layer. Finally, metal is deposited into the metal wire opening and the via opening to form the dual damascene structure of this invention.

摘要翻译： 一种用于形成金属互连的改进的双镶嵌工艺，包括以下步骤：提供具有导电层，第一介电层和已形成在其上的第一掩模层的半导体衬底。 第一电介质层由低k电介质材料制成。 在第一掩模层上形成第一氮氧化硅（SiON）层。 接下来，对第一氮氧化硅层进行构图，然后使用第一氧氮化硅作为掩模蚀刻第一掩模层。 随后，在第一氮氧化硅上形成第二电介质层和第二掩模层。 第二电介质层可以由低k电介质材料制成。 接下来，在第二掩模层上形成第二氧氮化硅层。 此后，对第二氮氧化硅层进行构图，然后使用第二氮氧化硅层作为掩模蚀刻第二掩模层。 随后，使用第二掩模层作为掩模，蚀刻第二介电层以形成金属丝开口。 蚀刻在金属线开口处继续向下以在暴露导电层的第一介电层中形成通孔。 最后，将金属沉积到金属丝开口和通孔中以形成本发明的双镶嵌结构。

公开(公告)号：US6084304A

公开(公告)日：2000-07-04

申请号：US100769

申请日：1998-06-05

申请人： Yimin Huang ,  Tri-Rung Yew

发明人： Yimin Huang ,  Tri-Rung Yew

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L23/485

CPC分类号： H01L23/53228 ,  H01L2224/85375

摘要： A metallization structure comprises a semiconductor substrate and pre-formed multi-interconnect layer, which include a passivation layer deposited on the top copper layer of the multi-interconnect layer, a pad window, and a non-copper thin conductive film. The non-copper thin conductive film is deposited in the pad window to protect the top copper layer from exposure to the air. The non-copper thin conductive film includes aluminum, tantalum, TaN, TiN, or WN.

摘要翻译： 金属化结构包括半导体衬底和预成形的多互连层，其包括沉积在多互连层的顶部铜层上的钝化层，焊盘窗口和非铜薄导电膜。 非铜薄导电膜沉积在焊盘窗口中以保护顶部铜层不暴露于空气中。 非铜薄导电膜包括铝，钽，TaN，TiN或WN。

公开(公告)号：US6080660A

公开(公告)日：2000-06-27

申请号：US32682

申请日：1998-02-27

申请人： Kun-Chih Wang ,  Hsiao-Pang Chou ,  Wen-Yi Hsieh ,  Tri-Rung Yew

发明人： Kun-Chih Wang ,  Hsiao-Pang Chou ,  Wen-Yi Hsieh ,  Tri-Rung Yew

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/31116 ,  H01L21/76802 ,  H01L21/76805

摘要： A method for manufacturing a via structure comprising the steps of providing a semiconductor substrate, and then forming conductive line and dielectric layer over the substrate. Next, a photolithographic and a first etching operation are conducted so that an opening in the dielectric layer exposing the conductive line surface is formed. The first etching operation uses several etchants including fluorobutane, which has the highest concentration. Since there is a re-entrance structure at the bottom of the opening, a second etching operation is performed. In the second etching operation, a portion of the conductive line is etched for a fixed time interval to control the degree of etching. Consequently, a slanting surface is formed at the bottom of the opening and the re-entrance structure is eliminated. With a planarized bottom, step coverage of subsequently deposited material is increased.

摘要翻译： 一种用于制造通孔结构的方法，包括以下步骤：提供半导体衬底，然后在衬底上形成导电线和电介质层。 接下来，进行光刻和第一蚀刻操作，从而形成暴露导电线表面的电介质层中的开口。 第一蚀刻操作使用多种蚀刻剂，包括具有最高浓度的氟代丁烷。 由于在开口的底部存在再入口结构，因此进行第二蚀刻操作。 在第二蚀刻操作中，导电线的一部分被蚀刻固定的时间间隔以控制蚀刻程度。 因此，在开口的底部形成倾斜表面，并且消除了再入口结构。 在平坦化的底部，随后沉积材料的阶梯覆盖率增加。

公开(公告)号：US06078492A

公开(公告)日：2000-06-20

申请号：US128364

申请日：1998-08-03

申请人： Kuo-Tai Huang ,  Wen-Yi Hsieh ,  Tri-Rung Yew

发明人： Kuo-Tai Huang ,  Wen-Yi Hsieh ,  Tri-Rung Yew

IPC分类号： H01L27/108 ,  H01L21/02 ,  H01L21/8242 ,  H01G4/30 ,  H01G4/008

CPC分类号： H01L27/10852 ,  H01L28/82

摘要： A structure of a capacitor includes two gates and a commonly used source/drain region on a substrate. Then, a pitted self align contact window (PSACW) partly exposes the commonly used source/drain region. Then an glue/barrier layer and a lower electrode of the capacitor are over the PSACW. Then a dielectric thin film with a material having high dielectric constant is over the lower electrode. Then, an upper electrode is over the dielectric thin film to complete a capacitor, which has a structure of metal insulator metal with a shape like the PSACW.

摘要翻译： 电容器的结构包括两个栅极和在衬底上的常用源极/漏极区域。 然后，凹陷的自对准接触窗口（PSACW）部分地暴露常用的源极/漏极区域。 然后电容器的胶/阻挡层和下电极在PSACW之上。 然后，具有高介电常数的材料的电介质薄膜在下电极之上。 然后，上电极在电介质薄膜的上方，以完成电容器，该电容器具有类似于PSACW形状的金属绝缘体金属的结构。

公开(公告)号：US6013579A

公开(公告)日：2000-01-11

申请号：US176385

申请日：1998-10-21

申请人： Kun-Chih Wang ,  Tri-Rung Yew

发明人： Kun-Chih Wang ,  Tri-Rung Yew

IPC分类号： H01L21/768 ,  H01L21/00

CPC分类号： H01L21/76829 ,  H01L21/76802 ,  H01L21/76897

摘要： A self-aligned via process to prevent the via poisoning includes forming a hydrogen silsesquioxane layer on the substrate and over a pre-formed metal layer, forming an etching stop layer on the hydrogen silsesquioxane layer, forming an oxide layer on the etching stop layer, and then proceeding with a two-step etching process to form a via. The two-step etching process first patterns the oxide layer using a patterned photoresist layer as a mask, and then patterns the etching stop layer together with the hydrogen silsesquioxane layer using the patterned oxide layer as a mask. Because the etching stop layer prevents the hydrogen silsesquioxane layer from reacting with the oxygen plasma during the photoresist layer removal process, via poisoning is eliminated.

摘要翻译： 用于防止通路中毒的自对准通孔工艺包括在基板上和预成型的金属层上形成氢倍半硅氧烷层，在氢倍半硅氧烷层上形成蚀刻停止层，在蚀刻停止层上形成氧化物层， 然后进行两步蚀刻工艺以形成通孔。 两步蚀刻工艺首先使用图案化的光致抗蚀剂层作为掩模对氧化物层进行图案化，然后使用图案化氧化物层作为掩模，将蚀刻停止层与氢倍半硅氧烷层一起图案化。 因为蚀刻停止层防止在光致抗蚀剂层去除过程中氢倍半硅氧烷层与氧等离子体反应，消除了中毒。

公开(公告)号：US5998251A

公开(公告)日：1999-12-07

申请号：US975492

申请日：1997-11-21

申请人： H. J. Wu ,  Shih-Wei Sun ,  Jacob Chen ,  Tri-Rung Yew

发明人： H. J. Wu ,  Shih-Wei Sun ,  Jacob Chen ,  Tri-Rung Yew

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10808

摘要： An integrated circuit device having both an array of logic circuits and an array of embedded DRAM circuits is provided using a process that avoids some of the most significant processing challenges for embedded DRAM integration. Transfer FETs and wiring lines are provided for the embedded DRAM circuits and FETs are provided for the logic portions of the device in an initial phase of the process. The gate electrodes and source/drain regions of the logic FETs are subjected to a salicide process at this initial phase and a thick planarized oxide layer is provided over both the embedded DRAM regions and the logic circuit regions. Capacitors and logic interconnects are next formed using common etching, titanium nitride deposition and tungsten deposition steps. Contact vias are formed to expose each of the source drain regions of the DRAM transfer FETs and to expose select conductors within the logic circuits. A titanium nitride layer is deposited over the device and within the various contact vias through the planarized oxide layer. A capacitor dielectric layer is provided over the device and then the capacitor dielectric layer is selectively removed from at least the contact vias that become bit line contacts and logic interconnects. A layer of tungsten is deposited and patterned to provide upper capacitor electrodes and to complete the bit line contacts and logic interconnects. This first level tungsten layer also can provide bit line wiring. The 1/2 V.sub.cc potential for the upper capacitor electrodes can be provided to the circuit using a level of interconnect wiring also used by the logic circuits.

摘要翻译： 使用避免嵌入式DRAM集成的一些最重要的处理挑战的过程来提供具有逻辑电路阵列和嵌入式DRAM电路阵列的集成电路器件。 为嵌入式DRAM电路提供转移FET和布线，并且在该过程的初始阶段为器件的逻辑部分提供FET。 逻辑FET的栅极电极和源极/漏极区域在该初始阶段经受自对准硅化物处理，并且在嵌入式DRAM区域和逻辑电路区域上均设置厚平坦化的氧化物层。 接下来使用常规蚀刻，氮化钛沉积和钨沉积步骤形成电容器和逻辑互连。 形成接触通孔以暴露DRAM传输FET的每个源极漏极区域并暴露在逻辑电路内的选择导体。 氮化钛层通过平坦化的氧化物层沉积在器件上并在各种接触孔内。 在器件上提供电容器介电层，然后至少选择性地从形成位线接触和逻辑互连的接触孔中去除电容器介质层。 沉积钨层并图案化以提供上层电容器电极并完成位线接触和逻辑互连。 该第一级钨层也可以提供位线布线。 上电容器电极的+ E，fra 1/2 + EE Vcc电位可以使用也由逻辑电路使用的互连布线的电平提供给电路。