公开(公告)号：US08514640B2

公开(公告)日：2013-08-20

申请号：US13036525

申请日：2011-02-28

Applicant: Makoto Miakashi ,  Katsuaki Isobe ,  Noboru Shibata

Inventor： Makoto Miakashi ,  Katsuaki Isobe ,  Noboru Shibata

IPC: G11C7/00

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/3436

Abstract: A semiconductor memory device, in which interference between adjoining cells can be reduced and an expansion of a chip area can be suppressed, comprising: a memory cell array in which plural memory cells connected to plural word lines and plural bit lines are disposed in a matrix form; sense amplifiers each of which is to be connected to each of the bit lines; a control circuit which controls voltages of the word lines and the bit lines, and programs data into the memory cells or reads data from the memory cells; wherein the plural bit lines include at least a first, a second, a third and a fourth bit lines adjoining to each other, and the sense amplifiers include at least a first and a second sense amplifiers, a first and a fourth selection transistors which are provided between the first and the fourth bit lines and the first sense amplifier, and connect the first and the fourth bit lines to the first sense amplifier; and a second and a third selection transistors which are provided between the second and the third bit lines and the second sense amplifier, and connect the second and the third bit lines to the second sense amplifier.

Abstract translation: 一种半导体存储器件，其中可以减少相邻单元之间的干扰并且可以抑制芯片面积的扩大，其包括：存储单元阵列，其中连接到多个字线和多个位线的多个存储器单元被布置在矩阵中 形成; 读出放大器中的每一个将连接到每个位线; 控制电路，其控制字线和位线的电压，并将数据编程到存储器单元中或从存储器单元读取数据; 其中所述多个位线至少包括彼此相邻的第一，第二，第三和第四位线，并且所述读出放大器至少包括第一和第二读出放大器，第一和第四选择晶体管是 设置在第一和第四位线与第一读出放大器之间，并将第一和第四位线连接到第一读出放大器; 以及设置在第二和第三位线和第二读出放大器之间的第二和第三选择晶体管，并将第二和第三位线连接到第二读出放大器。

公开(公告)号：US20130145162A1

公开(公告)日：2013-06-06

申请号：US13524843

申请日：2012-06-15

Applicant: Yuji NAGAI ,  Taku Kato ,  Tatsuyuki Matsushita ,  Toshihiro Suzuki ,  Noboru Shibata

Inventor： Yuji NAGAI ,  Taku Kato ,  Tatsuyuki Matsushita ,  Toshihiro Suzuki ,  Noboru Shibata

IPC: H04L9/32

CPC classification number: H04L9/0816 ,  G11B20/00362 ,  G11B20/00427 ,  H04L9/0822 ,  H04L9/0833 ,  H04L9/0897 ,  H04L9/32 ,  H04L2209/601

Abstract: According to one embodiment, a device includes first and second data generator, a one-way function processor, and a data output interface. The first data generator generates a second key by encrypting a host constant with a first key in AES operation. The second data generator generates a session key by encrypting a random number with a second key in AES operation. The one-way function processor generates authentication information by processing secret identification information with the session key in one-way function operation. The data output interface outputs the encrypted secret identification information, a family key block, and the authentication information to outside of the device.

Abstract translation: 根据一个实施例，设备包括第一和第二数据生成器，单向功能处理器和数据输出接口。 第一个数据生成器通过AES操作中的第一个密钥加密主机常数来生成第二个密钥。 第二数据生成器通过在AES操作中用第二密钥加密随机数生成会话密钥。 单向功能处理器通过在单向功能操作中通过会话密钥处理秘密识别信息来生成认证信息。 数据输出接口将加密的秘密识别信息，家庭密钥块和认证信息输出到设备外部。

公开(公告)号：US20130142333A1

公开(公告)日：2013-06-06

申请号：US13524271

申请日：2012-06-15

Applicant: Yuji Nagai ,  Toshihiro Suzuki ,  Noboru Shibata ,  Taku Kato ,  Tatsuyuki Matsushita

Inventor： Yuji Nagai ,  Toshihiro Suzuki ,  Noboru Shibata ,  Taku Kato ,  Tatsuyuki Matsushita

IPC: H04L9/00

CPC classification number: H04L9/0816 ,  G11B20/00086 ,  G11B20/00115 ,  G11B20/0021 ,  G11B2220/2516 ,  G11B2220/60 ,  H04L9/0822 ,  H04L9/0833 ,  H04L9/0897 ,  H04L9/32 ,  H04L2209/601

Abstract: According to one embodiment, a device includes a storage and an authenticator. The storage includes a first area, a second area and a third area. The first area stores NKey and SecretID, the second area stores index information. E-SecretID is generated by SecretID. The third area stores FKB including information generated by FKey. The authenticator authenticates the external device. HKey is generated by an AES encryption calculating using NKey and HC. A SKey is generated by an AES encryption process using HKey and RN. A one-way conversion calculating is performed. E-SecretID, FKB and Oneway-ID are output to the external device. The index information is read from the second area.

Abstract translation: 根据一个实施例，一种设备包括存储器和认证器。 存储器包括第一区域，第二区域和第三区域。 第一个区域存储NKey和SecretID，第二个区域存储索引信息。 E-SecretID由SecretID生成。 第三个区域存储FKB，包括FKey生成的信息。 验证器验证外部设备。 HKey由使用NKey和HC的AES加密计算产生。 通过使用HKey和RN的AES加密过程生成SKey。 执行单向转换计算。 E-SecretID，FKB和Oneway-ID被输出到外部设备。 从第二区域读取索引信息。

公开(公告)号：US08406056B2

公开(公告)日：2013-03-26

申请号：US13329671

申请日：2011-12-19

Applicant: Noboru Shibata ,  Kenichi Imamiya

Inventor： Noboru Shibata ,  Kenichi Imamiya

IPC: G11C16/06

CPC classification number: G11C16/08 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/30

Abstract: A memory cell array has a structure in which a plurality of memory cells connected with word lines and bit lines and connected in series are arranged in a matrix form. A selection transistor selects the word lines. A control circuit controls potentials of the word lines and the bit lines in accordance with input data, and controls write, read and erase operations of data with respect to the memory cell. The selection transistor is formed on a well, and a first negative voltage is supplied to a well, a first voltage (the first voltage the first negative voltage) is supplied to a selected word line and a second voltage is supplied to a non-selected word line in the read operation.

Abstract translation: 存储单元阵列具有这样的结构，其中与字线和位线连接并且串联连接的多个存储单元以矩阵形式布置。 选择晶体管选择字线。 控制电路根据输入数据控制字线和位线的电位，并且控制数据相对于存储器单元的写入，读取和擦除操作。 选择晶体管形成在阱上，并且第一负电压被提供给阱，第一电压（第一电压第一负电压）被提供给所选择的字线，并且第二电压被提供给未选择的 字线在读操作。

公开(公告)号：US08289783B2

公开(公告)日：2012-10-16

申请号：US12948256

申请日：2010-11-17

Applicant: Noboru Shibata

Inventor： Noboru Shibata

IPC: G11C11/34 ,  G11C16/04

CPC classification number: G11C16/3454 ,  G11C16/0483 ,  G11C16/3459

Abstract: A memory cell array includes a plurality of memory cells, in which n (n is a natural number equal to 3 or larger) cells are simultaneously written. A control circuit controls the memory cell array. A conversion circuit converts data constituted of k (k is equal to n or smaller, and is a natural number equal to 3 or larger) bits stored in the memory cells into data of h (h is equal to k or larger, and is a natural number equal to 2 or larger) bits on the basis of a conversion rule.

Abstract translation: 存储单元阵列包括多个存储单元，其中n（n是等于3或更大的自然数）单元被同时写入。 控制电路控制存储单元阵列。 A转换电路将存储在存储单元中的k（k等于或小于等于3的自然数）构成的数据转换为h（h等于k或更大）的数据，并且是 自然数等于2或更大）比特。

公开(公告)号：US08270214B2

公开(公告)日：2012-09-18

申请号：US12840567

申请日：2010-07-21

Applicant: Noboru Shibata ,  Kazunori Kanebako

Inventor： Noboru Shibata ,  Kazunori Kanebako

IPC: G11C11/34

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3418 ,  G11C29/00 ,  G11C2211/5642 ,  G11C2211/5648

Abstract: A semiconductor memory device, in which a multi-bit region including multi-bit memory cells that store data of two or more bits and a region including memory cells that store data of bits that are less than the bits of the data stored in the multi-bit memory cells are installed, is provided, which can perform a high-speed writing and lengthen the life span of the product without increasing the storage capacity of the region of the memory cells storing the data of bits that are less than the bits of the data in the multi-bit memory cells. The semiconductor memory device includes a plurality of memory cells which store n-bit (where n is a natural number that is equal to or larger than 2) data for one cell. Among the plurality of memory cells, h-bit (h≦n) data is stored in a memory MLC of a first region MLB, and i-bit (i

Abstract translation: 一种半导体存储器件，其中包括存储两个或多个位的数据的多位存储器单元的多位区域和包括存储小于存储在多路复用器中的数据的位的数据的存储器单元的区域 提供了可以执行高速写入和延长产品寿命的位存储器单元，而不增加存储单元的存储容量，存储单元的存储容量小于位 数据在多位存储单元中。 半导体存储器件包括存储一个单元的n位（其中n是等于或大于2的自然数）数据的多个存储单元。 在多个存储单元中，h位（h＆nlE; n）数据被存储在第一区域MLB的存储器MLC中，i位（i

公开(公告)号：US20120182800A1

公开(公告)日：2012-07-19

申请号：US13434951

申请日：2012-03-30

Applicant: Mitsuaki HONMA ,  Noboru Shibata

Inventor： Mitsuaki HONMA ,  Noboru Shibata

IPC: G11C16/04

CPC classification number: G11C16/26 ,  G11C16/06

Abstract: A memory cell array is connected to a word line and a bit line, and configured so that a plurality of memory cells storing one level of n levels (n is a natural number more than 4) in one memory cell are arrayed in a matrix. A control circuit controls a potential of the word line and the bit line in accordance with input data, and writs data in the memory cell. The control circuit applies a write voltage corresponding to write data to a memory cell. The write voltage differs for each write data. A verify operation is executed for each write data after a write voltage application operation ends with respect to all n levels.

Abstract translation: 存储单元阵列连接到字线和位线，并且被配置为使得在一个存储单元中存储n个电平（n是大于4的自然数）的一个电平的多个存储单元被排列成矩阵。 控制电路根据输入数据控制字线和位线的电位，并将数据写入存储单元。 控制电路将对应于写入数据的写入电压施加到存储单元。 每个写入数据的写入电压不同。 在写入电压施加操作相对于所有n个电平结束之后，对每个写入数据执行验证操作。

公开(公告)号：US08194461B2

公开(公告)日：2012-06-05

申请号：US12985427

申请日：2011-01-06

Applicant: Yasukazu Kosaki ,  Noboru Shibata

Inventor： Yasukazu Kosaki ,  Noboru Shibata

IPC: G11C16/10

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5634

Abstract: A semiconductor memory device with NAND cell units arranged therein, the NAND cell unit including: a plurality of electrically rewritable and non-volatile memory cells connected in series; first and second select gate transistors disposed at the both ends of the NAND cell unit for coupling it to a bit line and a source line, respectively; and dummy cells disposed adjacent to the first and second select gate transistors in the NAND cell unit, wherein the dummy cells are set at a state with a threshold voltage higher than that of an erase state of the memory cell.

Abstract translation: 一种其中布置有NAND单元单元的半导体存储器件，所述NAND单元单元包括：串联连接的多个电可重写和非易失性存储单元; 设置在NAND单元单元的两端的第一和第二选择栅晶体管分别用于将其耦合到位线和源极线; 以及在NAND单元单元中与第一和第二选择栅极晶体管相邻设置的虚设单元，其中虚设单元被设置为具有比存储单元的擦除状态的阈值电压高的阈值电压的状态。

公开(公告)号：US20120092929A1

公开(公告)日：2012-04-19

申请号：US13329671

申请日：2011-12-19

Applicant: Noboru Shibata ,  Kenichi Imamiya

Inventor： Noboru Shibata ,  Kenichi Imamiya

IPC: G11C16/04

CPC classification number: G11C16/08 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/30

Abstract: A memory cell array has a structure in which a plurality of memory cells connected with word lines and bit lines and connected in series are arranged in a matrix form. A selection transistor selects the word lines. A control circuit controls potentials of the word lines and the bit lines in accordance with input data, and controls write, read and erase operations of data with respect to the memory cell. The selection transistor is formed on a well, and a first negative voltage is supplied to a well, a first voltage (the first voltage the first negative voltage) is supplied to a selected word line and a second voltage is supplied to a non-selected word line in the read operation.

Abstract translation: 存储单元阵列具有这样的结构，其中与字线和位线连接并且串联连接的多个存储单元以矩阵形式布置。 选择晶体管选择字线。 控制电路根据输入数据控制字线和位线的电位，并且控制数据相对于存储单元的写入，读取和擦除操作。 选择晶体管形成在阱上，并且第一负电压被提供给阱，第一电压（第一电压第一负电压）被提供给所选择的字线，并且第二电压被提供给未选择的 字线在读操作。

公开(公告)号：US20120054416A1

公开(公告)日：2012-03-01

申请号：US13050431

申请日：2011-03-17

Applicant: Naoki KOBAYASHI ,  Mitsuaki Honma ,  Noboru Shibata

Inventor： Naoki KOBAYASHI ,  Mitsuaki Honma ,  Noboru Shibata

IPC: G06F12/02

CPC classification number: G11C11/5628

Abstract: According to one embodiment, a system includes a memory, a controller which controls an operation of the memory in a data program, and data bus which connects the memory to the controller. The memory comprises a memory cell array with memory cells which have a bit assignment to 2x (x is an integer number of 3 or more) threshold distributions, each memory cell storing x bits, and a control circuit which controls the data program of x bits to the memory cells. The controller comprises a first step generating y bit (y is an integer number and y

Abstract translation: 根据一个实施例，系统包括存储器，控制数据程序中的存储器的操作的控制器以及将存储器连接到控制器的数据总线。 存储器包括具有存储器单元的存储器单元阵列，其具有位分配为2x（x为3或更多的整数）阈值分布，每个存储单元存储x位，以及控制电路，其控制x位数据程序 到记忆体细胞。 控制器包括基于x位产生y位（y为整数和y