公开(公告)号：US20080115030A1

公开(公告)日：2008-05-15

申请号：US11599992

申请日：2006-11-15

Applicant: Thomas Hein ,  Rex Kho ,  Aaron John Nygren

Inventor： Thomas Hein ,  Rex Kho ,  Aaron John Nygren

IPC: H03M13/03

CPC classification number: H03M5/145

Abstract: An information transmitting apparatus is described. An interface includes a first input for a valid data word, a second input for an information to be transmitted, and an output, wherein the interface provides the data word or a data word recognizable as an invalid data word at the output, depending on the information. Accordingly, an information receiving apparatus comprises an interface comprising an input for a data word and an output for an information, wherein the interface derives the information depending on whether the data word is a valid data word or an invalid data word.

Abstract translation: 描述信息发送装置。 接口包括用于有效数据字的第一输入，用于要发送的信息的第二输入和输出，其中接口提供数据字或在输出端可被识别为无效数据字的数据字，这取决于 信息。 因此，信息接收装置包括包括用于数据字的输入和用于信息的输出的接口，其中接口根据数据字是有效数据字还是无效数据字导出信息。

公开(公告)号：US07324423B2

公开(公告)日：2008-01-29

申请号：US10451147

申请日：2002-10-25

Applicant: Yoichiro Sako ,  Akiya Saito ,  Yoshinobu Usui ,  Yoriaki Kanada ,  Tomihiro Nakagawa ,  Tatsuya Inokuchi ,  Shunsuke Furukawa ,  Takashi Kihara

Inventor： Yoichiro Sako ,  Akiya Saito ,  Yoshinobu Usui ,  Yoriaki Kanada ,  Tomihiro Nakagawa ,  Tatsuya Inokuchi ,  Shunsuke Furukawa ,  Takashi Kihara

IPC: G11B5/09

CPC classification number: G11B7/261 ,  G11B20/10 ,  G11B20/1426 ,  G11B2020/1438 ,  H03M5/145

Abstract: The present invention is relative with a method for recording further data on a recording medium on which there re pre-recorded data obtained on modulating M-bit data to N-bit data, where M

Abstract translation: 本发明与用于在将M位数据调制获得的预先记录的数据转换为N位数据的记录介质上记录另外的数据的方法相关，其中M

公开(公告)号：US07321320B2

公开(公告)日：2008-01-22

申请号：US11497260

申请日：2006-08-02

Applicant: Hiroyuki Shine

Inventor： Hiroyuki Shine

IPC: H03M7/00

CPC classification number: G11B20/1426 ,  G11B2020/1457 ,  H03M5/145

Abstract: A digital sum value (DSV) control apparatus inserts a DC control bit for each DC control block. The apparatus includes a first DSV accumulated value comparator for setting a target flag to a DC control bit for a first DC control block, a second DSV accumulated value comparator for comparing a first DSV accumulated value accumulated and calculated from DSV values of the first DC control block with a second DSV accumulated value accumulated and calculated from DSV values of a plurality of DC control blocks subsequent to the first DC control block, and a DC control bit determination output section for determining a value of a DC control bit for the first control block according to an output of the first and the second DSV accumulated value comparators.

Abstract translation: 数字和值（DSV）控制装置插入用于每个DC控制块的DC控制位。 该装置包括用于将目标标志设置为用于第一DC控制块的DC控制位的第一DSV累加值比较器，用于根据第一DC控制块的DSV值累积和计算的第一DSV累加值进行比较的第二DSV累加值比较器 具有从第一DC控制块之后的多个DC控制块的DSV值累积和计算的具有第二DSV累加值的块，以及用于确定第一控制块的DC控制位的值的DC控制位确定输出部分 根据第一和第二DSV累加值比较器的输出。

公开(公告)号：US20080001792A1

公开(公告)日：2008-01-03

申请号：US11819392

申请日：2007-06-27

Applicant: Yosuke Kondo ,  Kenji Yoshida

Inventor： Yosuke Kondo ,  Kenji Yoshida

IPC: H03M7/34

CPC classification number: H03M13/1102 ,  G11B20/10055 ,  G11B20/10296 ,  G11B20/1426 ,  H03M5/145 ,  H03M13/31

Abstract: There is provided an apparatus which obtains a circumstance where LDPC codes are interleaved without damaging modulation rules and thereby a correction ability of LDPC encoding and decoding method is fully exhibited. The apparatus includes an RLL rule applying section which modulates user data by applying an RLL rule to the user data and thereby obtains RLL encoded sequence data, an interleave section which interleaves the RLL encoded sequence data and thereby obtains interleaved sequence data, an LDPC parity generating section which subjects the interleaved sequence data to LDPC encoding processing and thereby obtains LDPC parity sequence data, an inserting section which inserts parity of the LDPC parity sequence data in the RLL encoded sequence data in a distribution manner and thereby obtains output data, and an output section which records or transmits the output data.

Abstract translation: 提供了一种获得LDPC码被交错而不损害调制规则的情况的装置，从而充分展示了LDPC编码和解码方法的校正能力。 该装置包括RLL规则应用部分，其通过对用户数据应用RLL规则来调制用户数据，从而获得RLL编码序列数据，交织部分，其对RLL编码序列数据进行交织，从而获得交织序列数据，LDPC奇偶校验产生 对交错序列数据进行LDPC编码处理，从而获得LDPC奇偶校验序列数据;插入部分，以分配方式将LDPC奇偶校验序列数据的奇偶校验插入RLL编码序列数据中，从而获得输出数据;输出部分 记录或传输输出数据的部分。

公开(公告)号：US20070279264A1

公开(公告)日：2007-12-06

申请号：US11787404

申请日：2007-04-16

Applicant: Toshiyuki Nakagawa

Inventor： Toshiyuki Nakagawa

IPC: H03M5/00

CPC classification number: G11B20/1426 ,  G11B2020/1457 ,  H03M5/145

Abstract: Disclosed herein is a modulation apparatus including: first conversion means for converting a portion included in processed data as a portion matching a first data pattern into a first code pattern in accordance with a first table associating an even/odd-characteristic retaining conversion pattern used as the first data pattern with the first code pattern; second conversion means for converting a portion included in processed data as a portion matching a second data pattern into a second code pattern in accordance with a second table associating an even/odd-characteristic retention violating conversion pattern used as the second data pattern with the second code pattern; and select means for selecting either the first code pattern or the second code pattern, wherein, if a DSV control bit has been inserted into the processed data, a process carried out by the second conversion means to convert the portion into the second code pattern is inhibited.

Abstract translation: 这里公开了一种调制装置，包括：第一转换装置，用于根据第一表将第一数据模式中匹配第一数据模式的部分包括在处理数据中的部分转换为第一表，该第一表将所用的偶/奇特性保持转换模式用作 具有第一码模式的第一数据模式; 第二转换装置，用于根据将用作第二数据模式的偶/奇特性保留违反转换模式与第二数据模式相关联的第二表将第二数据模式中匹配第二数据模式的部分包括在处理数据中的部分转换为第二数据模式 代码模式; 以及选择装置，用于选择第一编码模式或第二编码模式，其中，如果已经将DSV控制位插入到处理的数据中，则由第二转换装置执行的将该部分转换成第二编码模式的处理是 抑制。

公开(公告)号：US07301482B1

公开(公告)日：2007-11-27

申请号：US10872098

申请日：2004-06-17

Applicant: Mats Oberg

Inventor： Mats Oberg

IPC: H03M5/00

CPC classification number: H03M5/145

Abstract: Methods, algorithms, software, circuits, architectures, and systems for conditionally encoding information and processing conditionally encoded information. The present invention takes advantage of codes where most randomly selected data units fulfill the coding constraints. Thus, only those data units that need encoding (i.e., that do not fulfill coding constraints) are encoded, and those data units that do not need encoding (i.e., that fulfill coding constraints) are not encoded. By doing so, one may increase the density, bandwidth and/or gain of data communications, increase the error checking and/or correcting capabilities of a data communications system, and/or reduce interference in a multi-user system.

Abstract translation: 方法，算法，软件，电路，架构和系统，用于有条件地编码信息和处理有条件编码的信息。 本发明利用大多数随机选择的数据单元满足编码约束的代码。 因此，仅编码需要编码的那些数据单元（即，不满足编码约束）的那些数据单元被编码，并且不对不需要编码的那些数据单元（即，满足编码约束）进行编码。 通过这样做，可以增加数据通信的密度，带宽和/或增益，增加数据通信系统的错误检查和/或校正能力，和/或减少多用户系统中的干扰。

公开(公告)号：US07295138B2

公开(公告)日：2007-11-13

申请号：US11404906

申请日：2006-04-17

Applicant: Kees A. Schouhamer Immink

Inventor： Kees A. Schouhamer Immink

IPC: H03M5/00

CPC classification number: H03M5/04 ,  G11B20/1426 ,  H03M5/145

Abstract: In the coding device and method, m-bit information words are converted into n-bit code words such that the coding rate m/n is greater than ⅔. The n-bit code words are divided into a first type and a second type, and into coding states of a first kind and a second kind such that an m-bit information word is converted into an n-bit code word of the first or second kind if the previous m-bit information word was converted into an n-bit code word of the first type and is converted into an n-bit code word of the first kind if the previous m-bit information word was converted into an n-bit code word of the second type. In one embodiment, n-bit code words of the first type end in zero, n-bit code words of the second type end in one, n-bit code words of the first kind start with zero, and n-bit code words of the second kind start with zero or one. Furthermore, in the embodiments, the n-bit code words satisfy a dk-constraint of (1,k) such that a minimum of 1 zero and a maximum of k zeros falls between consecutive ones. The coding device and method are employed to record information on a recording medium and thus create the recording medium. The coding device and method are further employed to transmit information. In the decoding method and apparatus, n-bit code words are decoded into m-bit information words. The decoding involves determining the state of a next n-bit code word, and based on the state determination, the current n-bit code word is converted into an m-bit information word. The decoding device and method are employed to reproduce information from a recording medium, and to receive information transmitted over a medium.

Abstract translation: 在编码装置和方法中，m位信息字被转换成n位码字，使得编码率m / n大于2/3。 n位码字被分为第一类型和第二类型，并且分为第一种类型和第二类型的编码状态，使得m位信息字被转换成第一类型和第二类型的n位代码字， 如果先前的m位信息字被转换成第一类型的n位码字，并且如果先前的m位信息字被转换为n，则将其转换成第一类的n位码字的第二种 - 第二种类型的位代码字。 在一个实施例中，第一类型的n比特码字结束为零，第二类型的n比特码字一端结束，第一类的n比特码字从零开始，并且n比特码字为 第二种以零或一开始。 此外，在实施例中，n位码字满足（1，k）的dk约束，使得1个零的最小值和k个零的最大值落在连续的0之间。 采用编码装置和方法将信息记录在记录介质上，从而创建记录介质。 编码装置和方法进一步用于传送信息。 在解码方法和装置中，n位码字被解码成m位信息字。 解码涉及确定下一个n位代码字的状态，并且基于状态确定，将当前的n位代码字转换成m位信息字。 解码装置和方法用于从记录介质再现信息，并且接收通过介质发送的信息。

公开(公告)号：US07289046B2

公开(公告)日：2007-10-30

申请号：US10483622

申请日：2003-05-12

Applicant: Yoichiro Sako ,  Toru Aida ,  Tatsuya Inokuchi ,  Akiya Saito ,  Takashi Kihara ,  Tatsushi Sano ,  Yoriaki Kanada ,  Yoshiro Miyoshi ,  Shunsuke Furukawa ,  Yoshinobu Usui ,  Toshihiko Senno

Inventor： Yoichiro Sako ,  Toru Aida ,  Tatsuya Inokuchi ,  Akiya Saito ,  Takashi Kihara ,  Tatsushi Sano ,  Yoriaki Kanada ,  Yoshiro Miyoshi ,  Shunsuke Furukawa ,  Yoshinobu Usui ,  Toshihiko Senno

IPC: H03M7/00

CPC classification number: H03M7/46 ,  G11B20/00086 ,  G11B20/1426 ,  G11B2020/1287 ,  G11B2020/1457 ,  G11B2020/1461 ,  G11B2020/1469 ,  G11B2020/184 ,  H03M5/145

Abstract: A recording method for converting m-bit data into n-bit (where n>m) data whose run length is restricted and recording the converted data on a recording medium, the recording method comprising the step of selecting first n-bit data according to an immediately preceded n-bit data, first n-bit data immediately followed thereby, and second n-bit data immediately followed thereby so that the cumulative value of DC components per unit time becomes small.

Abstract translation: 一种用于将m比特数据转换成游程长度受限的n比特（其中n> m）数据并将转换的数据记录在记录介质上的记录方法，所述记录方法包括以下步骤：根据 紧随其后的n位数据，紧随其后的第一n位数据和紧随其后的第二n位数据，使得每单位时间的DC分量的累积值变小。

公开(公告)号：US07286065B1

公开(公告)日：2007-10-23

申请号：US11166425

申请日：2005-06-24

Applicant: Mats Oberg

Inventor： Mats Oberg

IPC: H03M7/00

CPC classification number: H03M5/145

Abstract: A method and apparatus reduces a DC level of an input word. The input word is divided into a plurality of components that include n symbols. The n symbols of the components are summed for each component. The component is encoded into a substitute component if a sum for the component exceeds a threshold. The components having a sum that does exceed the threshold are combined with at least one substitute component into an output word. An output word template is selected based on a number of substitute components and on a position that the substitute components originally occupied in the input word. The substitute components are inserted in the output word template. The components that have a sum that does not exceed the threshold are inserted in the output word template. Address and indicator symbols are inserted in the output word.

Abstract translation: 方法和装置降低输入字的直流电平。 输入字被分成包括n个符号的多个分量。 组件的n个符号对于每个组件相加。 如果组件的和超过阈值，则组件被编码为替代组件。 具有超过阈值的和的分量与至少一个替代组件组合成输出字。 基于替代组件的数量和替代组件最初在输入单词中占据的位置来选择输出单词模板。 替代组件插入到输出单词模板中。 具有不超过阈值的和的组件插入到输出单词模板中。 地址和指示符符号插入输出字。

公开(公告)号：US07283592B2

公开(公告)日：2007-10-16

申请号：US11525484

申请日：2006-09-22

Applicant: Toshiyuki Nakagawa ,  Yoshihide Shimpuku ,  Tatsuya Narahara

Inventor： Toshiyuki Nakagawa ,  Yoshihide Shimpuku ,  Tatsuya Narahara

IPC: H04B14/04

CPC classification number: G11B20/1426 ,  G11B20/1403 ,  G11B2020/1287 ,  G11B2020/1453 ,  G11B2020/1457 ,  H03M5/145 ,  H04L7/0083 ,  H04L7/041 ,  H04L7/044

Abstract: A digital sync signal added in a modulator to a train of codes having a digital sum value, and detected in a demodulator. The digital sync signal has a pattern that breaks a maximum run and a pattern that preserves a minimum run and a maximum run. The digital sync signal has a bit that is selectively determined to be a “0” or a “1” for controlling the digital sum value of the train of codes. The minimum run is repeated no more than a predetermined number of times irrespective of whether the digital sync signal includes the minimum run.

Abstract translation: 将调制器中的数字同步信号加到具有数字和值的代码串中，并在解调器中检测。 数字同步信号具有断开最大运行的模式和保持最小运行和最大运行的模式。 数字同步信号具有选择性地被确定为“0”或“1”的位，用于控制代码列的数字和值。 无论数字同步信号是否包括最小运行，最小运行重复不超过预定次数。