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1154 条记录 (耗时 0.031 秒)

    Phase detector devices and corresponding time-interleaving systems
    61.
    发明授权
    Phase detector devices and corresponding time-interleaving systems 有权

    公开(公告)号：US11750207B2

    公开(公告)日：2023-09-05

    申请号：US17722749

    申请日：2022-04-18

    申请人： Marvell Asia Pte Ltd.

    发明人： Ray Luan Nguyen ,  Geoffrey Hatcher

    IPC分类号： H03M1/12 ,  H03M1/28 ,  H03M1/36 ,  H03M1/06

    CPC分类号： H03M1/1215 ,  H03M1/0626 ,  H03M1/1255 ,  H03M1/282 ,  H03M1/362

    摘要： A multi-instance time-interleaving (TI) system and method of operation therefor. The system includes a plurality of TI devices, each with a plurality of clock generation units (CGUs) coupled to an interleaver network. Within each TI device, the plurality of CGUs provides a plurality of clock signals needed by the interleaver network. A phase detector device is coupled to the plurality of TI devices and configured to determine any phase differences between the clock signals of a designated reference TI device and the corresponding clock signals of each other TI device. To determine the phase differences, the phase detector can use a logic comparator configuration, a time-to-digital converter (TDC) configuration, or an auto-correlation configuration. The phases of the clock signals of each other TI device can be aligned to the reference TI device using internal phase control, retimers, delay cells, finite state machines, or the like.

    Methods and Apparatus for Preamble Detection in A Communication Network
    63.
    发明公开
    Methods and Apparatus for Preamble Detection in A Communication Network 审中-公开

    公开(公告)号：US20230269204A1

    公开(公告)日：2023-08-24

    申请号：US18141468

    申请日：2023-05-01

    申请人： Marvell Asia Pte, Ltd.

    发明人： Hyun Soo Cheon

    IPC分类号： H04L49/90 ,  H04W48/08 ,  G06F16/23 ,  H04L27/00

    CPC分类号： H04L49/90 ,  H04W48/08 ,  G06F16/2379 ,  H04L27/0014 ,  H04L2027/0095

    摘要： Methods and apparatus for preamble detection in a communication network are disclosed. In an exemplary embodiment, a method includes retrieving parameters from a parameter database, filling a buffer of preamble data received in an uplink transmission from user equipment, and frequency shifting the buffer of preamble data based on one or more first parameters to generate frequency shifted data. The method also includes oversampling the frequency shifted data to generates oversampled data, downsampling the over sampled data based on one or more second parameters to generate preamble samples, and updating the parameter database with updated values for the one or more first and second parameters. The method also includes repeating all the operations until a selected amount of preamble samples is obtained.

    Write timing for RRO field in a constant density servo system
    66.
    发明授权
    Write timing for RRO field in a constant density servo system 有权

    公开(公告)号：US11721363B2

    公开(公告)日：2023-08-08

    申请号：US17811990

    申请日：2022-07-12

    申请人： Marvell Asia Pte, Ltd.

    发明人： Supaket Katchmart

    IPC分类号： G11B19/04 ,  G11B5/012 ,  G11B5/55 ,  G11B5/596 ,  G11B19/14

    CPC分类号： G11B19/041 ,  G11B5/012 ,  G11B5/5526 ,  G11B5/59616 ,  G11B19/14 ,  G11B2220/2516

    摘要： A method for writing repeatable run-out data, representing a recurring contribution to position error, to a rotating constant-density magnetic storage medium, includes repeating, for each respective track at a respective radius of the constant-density magnetic storage medium, (1) determining a respective track pattern frequency based on track location and desired data density, (2) locating a position in a respective servo wedge on the respective track based on servo sync mark detection, (3) writing the repeatable run-out data to the respective servo wedge at a time delay, from the location of the position in the respective servo wedge, that is inversely proportional to the respective radius, to achieve a predetermined offset, and (4) repeating the determining, the locating and the writing for each servo wedge on the respective track of the constant-density magnetic storage medium.

    Methods and Apparatus for Control Channel Detection in An Uplink Shared Channel
    67.
    发明公开
    Methods and Apparatus for Control Channel Detection in An Uplink Shared Channel 审中-公开

    公开(公告)号：US20230247636A1

    公开(公告)日：2023-08-03

    申请号：US18132922

    申请日：2023-04-10

    申请人： Marvell Asia Pte, Ltd.

    发明人： Yuanbin Guo

    IPC分类号： H04W72/21 ,  H04L5/00 ,  H04W72/563

    CPC分类号： H04W72/21 ,  H04L5/0055 ,  H04L5/0046 ,  H04L5/0057 ,  H04W72/563

    摘要： Methods and apparatus for channel detection in an uplink shared control channel. In an exemplary embodiment, a method includes generating soft-combined bit streams for an acknowledgement (ACK) indicator, rank indicator (RI), and channel quality indicator (CQI) received in an uplink shared channel. The method also includes decoding the ACK, RI, and CQI soft-combined bit streams to generate Top-M decoded bit streams for each indicator, and generating Top-Q symbols for each indicator from the Top-M decoded bit streams for each indicator. The method also includes calculating metrics from the Top-Q symbols and uplink control information (UCI) symbols extracted from the uplink shared channel, combining the metrics to form a search space, and searching the search space to determine transmitted ACK, RI, and CQI bits.

    Implementing 128-bit SIMD operations on a 64-bit datapath
    68.
    发明授权
    Implementing 128-bit SIMD operations on a 64-bit datapath 有权

    公开(公告)号：US11709674B2

    公开(公告)日：2023-07-25

    申请号：US17072378

    申请日：2020-10-16

    申请人： Marvell Asia Pte, Ltd.

    发明人： David Kravitz ,  Manan Salvi ,  David A. Carlson

    IPC分类号： G06F9/30 ,  G06F9/38

    CPC分类号： G06F9/30036 ,  G06F9/3012 ,  G06F9/30014 ,  G06F9/30112 ,  G06F9/3887

    摘要： A method of implementing a processor architecture and corresponding system includes operands of a first size and a datapath of a second size. The second size is different from the first size. Given a first array of registers and a second array of registers, each register of the first and second arrays being of the second size, selecting a first register and corresponding second register from the first array and the second array, respectively, to perform operations of the first size. This allows a user, who is interfacing with the hardware processor through software, to provide data of the datapath bit-width instead of the register bit-width. Advantageously, the user is agnostic to the size of the registers.

    SYSTEM AND METHOD TO MANAGE POWER TO A DESIRED POWER PROFILE
    70.
    发明公开
    SYSTEM AND METHOD TO MANAGE POWER TO A DESIRED POWER PROFILE 审中-公开

    公开(公告)号：US20230229129A1

    公开(公告)日：2023-07-20

    申请号：US18123520

    申请日：2023-03-20

    申请人： Marvell Asia Pte Ltd

    发明人： Avinash Sodani ,  Ramacharan Sundararaman ,  James Eldredge ,  Richard Taylor

    IPC分类号： G05B19/042 ,  G06N20/00 ,  G06F1/3206

    CPC分类号： G05B19/042 ,  G06N20/00 ,  G06F1/3206 ,  G05B2219/2639

    摘要： A system includes a power profile engine, a power measurement engine, and a power throttling signal generator. The power profile engine receives a desired power profile, e.g., a first profile current average associated with a first time duration and a second profile current average associated with a second time duration. The power measurement engine measures current being drawn and generates a first running average for the measured currents for the first time duration and generates a second running average for the measured currents for the second time duration. The power throttling signal generator generates a first power throttling signal to throttle power in response to the first running average for the measured currents being greater than the first profile current average and generates a second power throttling signal to throttle power in response to the second running average for the measured currents being greater than the second profile current average.