公开(公告)号：US11995009B2

公开(公告)日：2024-05-28

申请号：US17469769

申请日：2021-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. Malladi ,  Hongzhong Zheng ,  Dimin Niu ,  Peng Gu

IPC: G06F13/16 ,  G06F7/544 ,  G06F9/30

CPC classification number: G06F13/1652 ,  G06F7/5443 ,  G06F9/30014 ,  G06F9/30036 ,  G06F13/1694

Abstract: A high bandwidth memory (HBM) system includes a first HBM+ card. The first HBM+ card includes a plurality of HBM+ cubes. Each HBM+ cube has a logic die and a memory die. The first HBM+ card also includes a HBM+ card controller coupled to each of the plurality of HBM+ cubes and configured to interface with a host, a pin connection configured to connect to the host, and a fabric connection configured to connect to at least one HBM+ card.

公开(公告)号：US20230119291A1

公开(公告)日：2023-04-20

申请号：US18081488

申请日：2022-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien Chang ,  Krishna T. Malladi ,  Dimin Niu ,  Hongzhong Zheng

IPC: G06F12/0875 ,  G06F13/16 ,  G06F13/12

Abstract: A method of processing in-memory commands in a high-bandwidth memory (HBM) system includes sending a function-in-HBM instruction to the HBM by a HBM memory controller of a GPU. A logic component of the HBM receives the FIM instruction and coordinates the instructions execution using the controller, an ALU, and a SRAM located on the logic component.

公开(公告)号：US11475102B2

公开(公告)日：2022-10-18

申请号：US16407064

申请日：2019-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongyan Jiang ,  Dimin Niu ,  Hongzhong Zheng

IPC: G06F17/16 ,  G06F9/38 ,  G06F9/50

Abstract: An adaptive matrix multiplier. In some embodiments, the matrix multiplier includes a first multiplying unit a second multiplying unit, a memory load circuit, and an outer buffer circuit. The first multiplying unit includes a first inner buffer circuit and a second inner buffer circuit, and the second multiplying unit includes a first inner buffer circuit and a second inner buffer circuit. The memory load circuit is configured to load data from memory, in a single burst of a burst memory access mode, into the first inner buffer circuit of the first multiplying unit; and into the first inner buffer circuit of the second multiplying unit.

公开(公告)号：US11294571B2

公开(公告)日：2022-04-05

申请号：US16819032

申请日：2020-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng ,  Sun Young Lim ,  Indong Kim ,  Jangseok Choi

IPC: G06F12/00 ,  G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  G11C5/04 ,  G11C11/406 ,  G11C29/04

Abstract: A memory module includes a memory array, an interface and a controller. The memory array includes an array of memory cells and is configured as a dual in-line memory module (DIMM). The DIMM includes a plurality of connections that have been repurposed from a standard DIMM pin out configuration to interface operational status of the memory device to a host device. The interface is coupled to the memory array and the plurality of connections of the DIMM to interface the memory array to the host device. The controller is coupled to the memory array and the interface and controls at least one of a refresh operation of the memory array, control an error-correction operation of the memory array, control a memory scrubbing operation of the memory array, and control a wear-level control operation of the array, and the controller to interface with the host device.

公开(公告)号：US11079936B2

公开(公告)日：2021-08-03

申请号：US15143248

申请日：2016-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mu-Tien Chang ,  Prasun Gera ,  Dimin Niu ,  Hongzhong Zheng

IPC: G06F3/06 ,  G06F15/78 ,  G06F9/30

Abstract: A 3D-stacked memory device including: a base die including a plurality of switches to direct data flow and a plurality of arithmetic logic units (ALUs) to compute data; a plurality of memory dies stacked on the base die; and an interface to transfer signals to control the base die.

公开(公告)号：US11010242B2

公开(公告)日：2021-05-18

申请号：US16276369

申请日：2019-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dimin Niu ,  Mu-Tien Chang ,  Hongzhong Zheng ,  Hyun-Joong Kim ,  Won-hyung Song ,  Jangseok Choi

IPC: G06F11/00 ,  G06F11/10 ,  G11C5/04 ,  G11C29/42 ,  G11C29/52

Abstract: A method of correcting a memory error of a dynamic random-access memory module (DRAM) using a double data rate (DDR) interface, the method includes conducting a memory transaction including multiple bursts with a memory controller to send data from data chips of the DRAM to the memory controller, detecting one or more errors using an ECC chip of the DRAM, determining a number of the bursts having the errors using the ECC chip of the DRAM, determining whether the number of the bursts having the errors is greater than a threshold number, determining a type of the errors, and directing the memory controller based on the determined type of the errors, wherein the DRAM includes a single ECC chip per memory channel.

公开(公告)号：US10732866B2

公开(公告)日：2020-08-04

申请号：US15595887

申请日：2017-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dimin Niu ,  Shuangchen Li ,  Bob Brennan ,  Krishna T. Malladi ,  Hongzhong Zheng

IPC: G06F3/06 ,  G11C11/4096 ,  G06F15/78

Abstract: A processor includes a plurality of memory units, each of the memory units including a plurality of memory cells, wherein each of the memory units is configurable to operate as memory, as a computation unit, or as a hybrid memory-computation unit.

公开(公告)号：US20200097417A1

公开(公告)日：2020-03-26

申请号：US16194219

申请日：2018-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. Malladi ,  Hongzhong Zheng ,  Dimin Niu ,  Peng Gu

IPC: G06F13/16 ,  G06F7/544 ,  G06F9/30

Abstract: A high bandwidth memory (HBM) system includes a first HBM+ card. The first HBM+ card includes a plurality of HBM+ cubes. Each HBM+ cube has a logic die and a memory die. The first HBM+ card also includes a HBM+ card controller coupled to each of the plurality of HBM+ cubes and configured to interface with a host, a pin connection configured to connect to the host, and a fabric connection configured to connect to at least one HBM+ card.

公开(公告)号：US10592114B2

公开(公告)日：2020-03-17

申请号：US15213386

申请日：2016-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng ,  Sun Young Lim ,  Indong Kim ,  Jangseok Choi

IPC: G06F12/00 ,  G06F3/06 ,  G11C29/52 ,  G06F11/10 ,  G11C29/04 ,  G11C11/406 ,  G11C5/04

Abstract: A memory module includes a memory array, an interface and a controller. The memory array includes an array of memory cells and is configured as a dual in-line memory module (DIMM). The DIMM includes a plurality of connections that have been repurposed from a standard DIMM pin out configuration to interface operational status of the memory device to a host device. The interface is coupled to the memory array and the plurality of connections of the DIMM to interface the memory array to the host device. The controller is coupled to the memory array and the interface and controls at least one of a refresh operation of the memory array, control an error-correction operation of the memory array, control a memory scrubbing operation of the memory array, and control a wear-level control operation of the array, and the controller to interface with the host device.

公开(公告)号：US10558388B2

公开(公告)日：2020-02-11

申请号：US15169609

申请日：2016-05-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dimin Niu ,  Mu-Tien Chang ,  Hongzhong Zheng ,  Craig Hanson ,  Sun Young Lim ,  Indong Kim

IPC: G06F3/06

Abstract: A memory system includes: one or more memory modules, each comprising a plurality of memory devices having corresponding write commit policies; and one or more memory controllers coupled to the one or more memory modules, the one or more memory controllers having a configurable write operation protocol to operate with the memory devices according to the corresponding write commit policies.