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公开(公告)号：US20240371316A1
公开(公告)日：2024-11-07
申请号：US18777590
申请日：2024-07-19
Inventor： Miao LIU , Xueguang HAO , Jingbo XU , Xing YAO , Jingquan WANG , Xinyin WU , Xinguo LI , Zhichong WANG
IPC: G09G3/32 , G09G3/3208 , G09G3/3266
Abstract: A display substrate, including a scan drive control circuit including an input circuit, an output control circuit, and an output circuit; the input circuit is configured to transmit a signal of the signal input terminal to the output control circuit and a signal of the first clock signal terminal or the first voltage terminal to the output control circuit; the output control circuit is configured to store a signal of the first signal terminal, and transmit a signal of the second signal terminal to the first node; or, the output control circuit is configured to store a signal of the second clock signal terminal, and transmit a signal of the second voltage terminal to the first node; the output circuit is configured to output a signal of the first voltage terminal to the signal output terminal, or output the signal of the second voltage terminal to the signal output terminal.
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公开(公告)号：US20240324372A1
公开(公告)日：2024-09-26
申请号：US18034076
申请日：2022-04-19
Inventor： Yuxin ZHANG , Lili DU , Jingquan WANG , Xueguang HAO , Xinguo LI
IPC: H10K59/131 , H10K59/121 , H10K59/65 , H10K59/88
CPC classification number: H10K59/1315 , H10K59/1213 , H10K59/65 , H10K59/88
Abstract: A display substrate includes a base substrate (100), multiple first pixel circuits (11), multiple second active pixel circuits (12), multiple first light-emitting elements (13), multiple second light-emitting elements (14) and at least one first data line (21). The first data line (21) includes a first sub-data line (211) and a second sub-data line (212). The first sub-data line (211) is electrically connected with the multiple first pixel circuits (11) arranged along a first direction (D1), and the second sub-data line (212) is electrically connected with the multiple second active pixel circuits (12) arranged along the first direction (D1). The first sub-data line (211) and the second sub-data line (212) are electrically connected through a first transfer line (214), and the first transfer line (214) is located in a peripheral region (BB) and between a signal access region (B14) and a display region (AA).
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公开(公告)号：US20240260321A1
公开(公告)日：2024-08-01
申请号：US18020418
申请日：2022-02-25
Inventor： Jingjing XU , Fei FANG , Puyu QI , Kening ZHENG , Jun YAN , Kemeng TONG , Xueguang HAO , Pan LI , Yuxin ZHANG , Chunyan LI , Jingquan WANG , Xinguo LI
IPC: H10K59/122 , G06F3/041 , G06F3/044 , G09G3/3233 , H10K59/131 , H10K59/40
CPC classification number: H10K59/122 , G06F3/0412 , G09G3/3233 , H10K59/131 , H10K59/40 , G06F3/0443 , G06F3/0446 , G09G2300/0819 , G09G2300/0842 , G09G2300/0861 , G09G2310/08
Abstract: A display substrate includes a base substrate including a display region and a frame region, multiple pixel circuits, first light-emitting elements and at least one first data line, located in a first sub-display region, multiple second light-emitting elements located in a second sub-display region. The display region includes a foldable first display region and second display region each including a first sub-display region and second sub-display region; multiple pixel circuits includes multiple first pixel circuits and second pixel circuits distributed among multiple first pixel circuits; at least one first pixel circuits is connected with at least one of multiple-first light-emitting elements; at least one of multiple second pixel circuits is connected with at least one of multiple second light-emitting elements; the first data line at least includes one sub-data line connected with the first pixel circuit and at least includes another sub-data line connected with the second pixel circuit.
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公开(公告)号：US20240215371A1
公开(公告)日：2024-06-27
申请号：US18596678
申请日：2024-03-06
Inventor： Chen XU , Xueguang HAO , Yong QIAO , Xinyin WU
IPC: H10K59/35 , H10K59/121 , H10K59/131
CPC classification number: H10K59/353 , H10K59/1213 , H10K59/1216 , H10K59/131
Abstract: There is provided a display substrate and a display device. The display substrate includes a first metal layer, a first insulating layer, a metal oxide layer, a second insulating layer and a second metal layer which are stacked; wherein the metal oxide layer comprises a first pattern, a second pattern and a capacitance pattern, the first metal layer comprises a first electrode plate, there is at least a first overlapping region between the first electrode plate and the capacitance pattern to form a first storage capacitor, the second metal layer comprises a second electrode plate, there is at least a second overlapping region between the second electrode plate on the base substrate and the capacitance pattern to form a second storage capacitor, and the first electrode plate and the second electrode plate have same potential.
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公开(公告)号：US20240172508A1
公开(公告)日：2024-05-23
申请号：US18551067
申请日：2022-08-24
Inventor： Jingbo XU , Xueguang HAO , Jingquan WANG , Xinyin WU , Lu BAI
IPC: H10K59/131 , G02F1/1362 , G02F1/1368 , G09G3/3233 , G09G3/3266 , G09G3/36 , H10K59/122 , H10K59/80
CPC classification number: H10K59/131 , G02F1/136286 , G02F1/1368 , G09G3/3233 , G09G3/3266 , G09G3/3677 , H10K59/122 , H10K59/80516 , H10K59/80522 , G09G2300/0426 , G09G2300/0819 , G09G2300/0842 , G09G2300/0861 , G09G2310/0286
Abstract: A display substrate and a display panel. The display substrate comprises: a base substrate, wherein the base substrate comprises a display area (10) and a peripheral area (20), which is located at at least one side of the display area (10). The display area (10) comprises pixel units (11), which are arranged in an array, first gate scanning signal lines (E1-Em) and second gate scanning signal lines (RT1-RTm); and the peripheral area (20) comprises a first scanning drive circuit (21), which is connected to the first gate scanning signal lines (E1-Em) by means of first connecting wirings (30), a second scanning drive circuit (22), which is connected to the second gate scanning signal lines (RT1-RTm) by means of second connecting wirings (40), first voltage signal lines (Evgh), which are configured to provide a first voltage, and second voltage signal lines (GNvgh), which are configured to provide a second voltage, wherein the second scanning drive circuit (22) is located at the side of the first scanning drive circuit (21) that is close to the display area (10). The ratio of a second resistance value to a first resistance value is less than the ratio of the average line width of the second voltage signal lines (GNvgh) to the average line width of the first voltage signal lines (Evgh). By means of the display substrate, a difference in a signal delay time brought about by different resistances of different connecting wirings can be reduced.
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Patent Agency Ranking
公开(公告)号：US20230096411A1
公开(公告)日：2023-03-30
申请号：US17052092
申请日：2020-04-11
Inventor： Xueguang HAO , Yong QIAO , Xinyin WU , Hongfei CHENG
IPC: H10K50/86 , H10K59/38 , H10K59/131 , H10K59/122
Abstract: Disclosed are an OLED display panel and a display device. The OLED display panel includes a substrate, a plurality of light emitting components arranged in an array, and a light resistance structure between the light emitting components. The light resistance structure prevents the reflected light of the emergent light from the light emitting components, from emitting out from one side of the substrate between the light emitting components.
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公开(公告)号：US20220216293A1
公开(公告)日：2022-07-07
申请号：US17609336
申请日：2021-02-25
Inventor： Yongda MA , Jianbo XIAN , Xueguang HAO , Yong QIAO
IPC: H01L27/32
Abstract: The present disclosure provides a lead arrangement structure for an OLED display device and a display device. The lead arrangement structure is disposed on a substrate of the display device. The substrate includes a display region and a lead region surrounding the display region. The lead arrangement structure includes first power lines disposed in the display region and second power lines disposed in the lead region, wherein each of the first power lines is electrically connected to a plurality of columns of sub-pixels, and one end of each of the second power lines is connected to a connection terminal on the substrate and the other end of the second power line is electrically connected to a plurality of the first power lines. The lead arrangement structure for the OLED display device and the display device according to the present disclosure can reduce the wiring workload of the power line, improve the utilization rate of the pixel space, and improve the display effect.
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公开(公告)号：US20220069056A1
公开(公告)日：2022-03-03
申请号：US17418810
申请日：2020-11-03
Inventor： Hongfei CHENG , Xueguang HAO
IPC: H01L27/32 , G02F1/1362 , G02F1/1368 , H01L27/02
Abstract: Provided is an array substrate, including: a first conductive wire, a second conductive wire and a first electrostatic protection unit, wherein the first electrostatic protection unit comprises a first thin-film transistor and a first capacitor; wherein a gate of the first thin-film transistor is suspended and is connected to a first electrode of the first thin-film transistor via the first capacitor, the first electrode of the thin-film transistor is connected to the first conductive wire, and a second electrode of the first thin-film transistor is connected to the second conductive wire.
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69.发明申请公开(公告)号：US20210335195A1
公开(公告)日：2021-10-28
申请号：US16475513
申请日：2019-01-08
Inventor： Jianbo XIAN , Chen XU , Xueguang HAO , Yong QIAO
IPC: G09G3/20
Abstract: A shift register unit, a circuit structure, a gate drive circuit, a drive circuit and a display device are provided. A shift register unit includes a substrate and an input circuit, a reset circuit, a first output circuit, a first output terminal, a first connection conductive portion connecting both the input circuit and the reset circuit, a second connection conductive portion connecting both the reset circuit and the first output circuit, and a third connection conductive portion connecting both the first output circuit and the first output terminal, all of which are on the substrate.
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公开(公告)号：US20210256913A1
公开(公告)日：2021-08-19
申请号：US17271319
申请日：2020-07-22
Inventor： Xueguang HAO , Yong QIAO , Xinyin WU
IPC: G09G3/3266 , H01L27/32 , H01L51/52
Abstract: An array substrate has a display area and a peripheral area located outside the display area. The display area includes two first sides that are substantially parallel and arc sides connected to ends of the first sides. The array substrate includes at least one gate driving circuit. Each gate driving circuit includes GOA units sequentially distributed along each arc side in at least one arc side and active GOA units sequentially distributed along a first side connected to the arc side. The GOA units includes at least one active GOA unit and at least one dummy GOA unit. Each active GOA unit is configured to provide a driving signal to at least one sub-pixel. A distance between two adjacent GOA units in the GOA units is approximately same as a distance between two adjacent active GOA units in the active GOA units.
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