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公开(公告)号：US11963429B2
公开(公告)日：2024-04-16
申请号：US17922197
申请日：2020-06-19
Inventor： Yu Wang , Yi Zhang , Tingliang Liu , Tinghua Shang , Huijuan Yang , Yang Zhou , Pengfei Yu , Linhong Han , Hao Zhang , Xiaofeng Jiang , Huijun Li
CPC classification number: H10K59/90 , G09G3/3208 , H01L24/32 , H10K59/82 , G09G2320/0204 , G09G2330/021 , H01L24/13 , H01L2224/13023 , H01L2224/32145
Abstract: A display module (10) includes: a display panel (12) and a circuit board (14) coupled to the display panel (12). The display panel (12) includes a driving chip (122) and a display unit (124); and the circuit board (14) includes a first filter element (142), wherein the first filter element (142) is coupled to the driving chip (122) and the display unit (124), and a direct current signal output by the driving chip (122) is filtered by the first filter element (142) and then transmitted to the display unit (124). The present disclosure also provides a display apparatus (100).
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公开(公告)号：US11955088B2
公开(公告)日：2024-04-09
申请号：US18086524
申请日：2022-12-21
Inventor： Lu Bai , Yang Zhou , Yi Qu , Chang Luo , Huijuan Yang , Yi Zhang , Junxiu Dai
IPC: G09G3/3266 , H10K59/121 , H10K59/131
CPC classification number: G09G3/3266 , H10K59/1213 , H10K59/1216 , H10K59/131
Abstract: A display substrate includes a base substrate, multiple sub-pixels, multiple first gate drive circuits, and at least one auxiliary structure. The base substrate includes a display region and a peripheral region located at a periphery of the display region. The multiple sub-pixels are located in the display region. The multiple first gate drive circuits and the at least one auxiliary structure are located in the peripheral region. The multiple first gate drive circuits are configured to provide first gate drive signals to the multiple sub-pixels. One auxiliary structure is disposed between adjacent first gate drive circuits.
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公开(公告)号：US11910669B2
公开(公告)日：2024-02-20
申请号：US17428979
申请日：2020-10-30
Inventor： Maoying Liao , Yang Zhou , Xin Zhang , Huijuan Yang
IPC: H10K59/40 , G09G3/3291 , H10K59/131 , H10K59/124 , H10K59/121 , H01L27/12 , G09G3/3258
CPC classification number: H10K59/131 , G09G3/3258 , G09G2300/0426 , G09G2300/0842
Abstract: An array substrate is provided. The array substrate includes a node connecting line in a same layer as a respective one of the plurality of voltage supply lines, connected to a first capacitor electrode through a first via, and connected to a semiconductor material layer through a second via; and an interference preventing block in a same layer as the second capacitor electrode. The respective one of the plurality of voltage supply lines is connected to the interference preventing block through a third via. The interference preventing block includes a first arm and a second arm. Along the first direction, a portion of the node connecting line at a position connecting to the semiconductor material layer through the second via is spaced apart from a first adjacent data line by the first arm, and is spaced apart from a second adjacent data line by the second arm.
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公开(公告)号：US11094765B2
公开(公告)日：2021-08-17
申请号：US16713977
申请日：2019-12-13
Inventor： Shun Zhang , Linhong Han , Yang Zhou , Mengmeng Du , Yue Teng
Abstract: The present disclosure relates to an array substrate, manufacturing method thereof, and a display panel. The array substrate includes a substrate, at least a first top gate TFT and at least a first bottom gate TFT disposed on the substrate and located in each sub-pixel region; a gate of the first top gate TFT and a gate of the first bottom gate TFT are formed in a same layer with same material, an active layer pattern of the first top gate TFT and an active layer pattern of the first bottom gate TFT are respectively arranged on two sides of the gate, and orthographic projections of the active layer pattern of the first top gate TFT and the active layer pattern of the first bottom gate TFT on the substrate are spaced from each other in a first direction.
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公开(公告)号：US09947273B2
公开(公告)日：2018-04-17
申请号：US15220080
申请日：2016-07-26
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Song Meng , Danna Song , Yang Zhou , Fei Yang
IPC: G09G3/3258
CPC classification number: G09G3/3258 , G09G3/20 , G09G2300/043 , G09G2300/0452 , G09G2320/0233
Abstract: The present disclosure provides a voltage drop compensation method, a voltage drop compensation device and a display device. The voltage drop compensation method includes steps of determining a voltage drop for a power signal corresponding to each subpixel set; determining a first equivalent brightness reduction value corresponding to the voltage drop; calculating an initial brightness value for each subpixel in the subpixel set; calculating a sum of the first equivalent brightness reduction value corresponding to the subpixel set and the initial brightness value as a target brightness value for each subpixel in the subpixel set; and generating a driving signal for each subpixel in accordance with the target brightness value for each subpixel in the subpixel set, and outputting the driving signal.
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Patent Agency Ranking
公开(公告)号：US20250089502A1
公开(公告)日：2025-03-13
申请号：US18955845
申请日：2024-11-21
Inventor： Maoying Liao , Yang Zhou , Xin Zhang , Huijuan Yang
IPC: H10K59/131 , G09G3/3258
Abstract: An array substrate is provided. The array substrate includes a node connecting line in a same layer as a respective one of the plurality of voltage supply lines, connected to a first capacitor electrode through a first via, and connected to a semiconductor material layer through a second via; and an interference preventing block in a same layer as the second capacitor electrode. Along the first direction, a portion of the node connecting line at a position connecting to the semiconductor material layer through the second via is spaced apart from a first adjacent data line by a first arm, and is spaced apart from a second adjacent data line by a second arm.
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公开(公告)号：US12225759B2
公开(公告)日：2025-02-11
申请号：US18510068
申请日：2023-11-15
Inventor： Yupeng He , Yang Zhou , Xin Zhang , Pengfei Yu , Xiaofeng Jiang , Yi Qu , Lulu Yang , Huijun Li , Meng Zhang
IPC: H10K50/844 , H10K59/12 , H10K59/121 , H10K59/122 , H10K59/124 , H10K59/65 , H10K71/00
Abstract: A display substrate, a manufacturing method thereof, and a display device are provided. A pixel region is provided with a light emission function layer on a base substrate of the display substrate, and a separation region is provided with at least one first barrier structure. The first barrier structure includes a stopper pattern and a first separation component. A side surface of the first separation component has a recess, and a portion of the light emission function layer extending to the separation region is disconnected on the side of the first separation component. The separation region is provided with an inorganic layer structure on the base substrate. The inorganic layer structure includes multiple stacked inorganic film layers, the stopper pattern is located between two adjacent inorganic film layers and the first separation component is located on a side of the inorganic layer structure away from the base substrate.
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公开(公告)号：US12193282B2
公开(公告)日：2025-01-07
申请号：US17419749
申请日：2020-09-10
Inventor： Xin Zhang , Yang Zhou , Junxiu Dai , Maoying Liao , Yi Zhang , Xiaoqing Shu , Hongwei Ma , Mengmeng Du , Rong Wang , Xiangdan Dong , Zhenhua Zhang , Shuangbin Yang , Bo Cheng , Yujing Li
IPC: H01L27/32 , H10K59/131 , H10K59/121
Abstract: A display substrate and a display device. In the display substrate, at least one of the inter-opening region, the first opening peripheral region and the second opening peripheral region includes a first virtual sub-pixel; the first signal line extends along a first direction and includes a first portion passing through the first opening peripheral region, the inter-opening region and the second opening peripheral region; the first portion passes through the first virtual sub-pixel, and the first virtual sub-pixel includes a first compensation capacitor, a first plate of the first compensation capacitor is in a same layer as the first portion of the first signal line and electrically connected with the first portion of the first signal line, and in a same layer as the second plate of the storage capacitor; the second plate is in a different layer from, insulated from, and overlaps with the first plate.
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公开(公告)号：US12144218B2
公开(公告)日：2024-11-12
申请号：US17297484
申请日：2020-08-10
Inventor： Linhong Han , Shikai Qin , Yi Zhang , Yang Zhou , Meng Zhang
IPC: H10K59/131
Abstract: Provided is a display substrate. In the display substrate, a base substrate includes a display region, a bending region and a pad region. A length of the display region in a first direction is greater than a length of the display region in a second direction. Since the pad region, the bending region and the display region are arranged along the second direction, the pad region is arranged on a side where a long boundary line of the display region is located, such that each signal line led into the display region from the pad region has a relatively short length in the display region.
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公开(公告)号：US12137585B2
公开(公告)日：2024-11-05
申请号：US17419741
申请日：2020-09-10
Inventor： Bo Zhang , Xiaoqing Shu , Zhenhua Zhang , Rong Wang , Zhenggang Wu , Xin Zhang , Yang Zhou , Junxiu Dai , Maoying Liao , Yi Zhang
IPC: H01L27/32 , H10K59/121 , H10K59/131 , H10K59/65 , G09G3/20 , G09G3/3233
Abstract: A display substrate and a display device. A first opening region includes a first opening and a first opening peripheral region surrounding the first opening; a display region surrounds the first opening region the first signal lines extend along the first direction; the second signal lines extend along a second direction; the second signal lines pass through the first opening peripheral region along the second direction, each second signal line includes a longitudinal winding portion in the first opening peripheral region; the longitudinal winding portion partially surrounds the first opening; the longitudinal winding portion closest to the first opening among longitudinal winding portion of the plurality of second signal lines is an edge longitudinal winding portion, and the first floating electrode is in a same layer as the edge longitudinal winding portion and is at a side of the edge longitudinal winding portion close to the first opening.
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