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61.发明授权公开(公告)号：US10886410B2
公开(公告)日：2021-01-05
申请号：US16393023
申请日：2019-04-24
Inventor： Yingbin Hu , Ce Zhao , Yuankui Ding , Wei Li , Wei Song , Luke Ding , Jun Liu , Liangchen Yan
IPC: H01L29/786 , H01L27/32 , H01L29/66
Abstract: Provided is a thin film transistor, including: a conductive light shielding layer; a metal oxide layer arranged on the light shielding layer; a buffer layer, an active layer, a gate insulating layer, a gate electrode, and an interlayer insulating layer arranged in sequence on the metal oxide layer, the interlayer insulating layer and the buffer layer comprising a first via hole and a second via hole for exposing the active layer, and a third via hole for exposing the metal oxide layer, in which a portion of the metal oxide layer exposed through the third via hole is a conductive portion, and other portions are insulative; and a source electrode and a drain electrode arranged on the interlayer insulating layer, in which the source electrode is connected to the active layer through the first via hole, and the drain electrode is connected to the active layer through the second via hole and connected to the conductive portion through the third via hole.
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公开(公告)号：US10680053B1
公开(公告)日：2020-06-09
申请号：US16441422
申请日：2019-06-14
Inventor： Yingbin Hu , Liangchen Yan , Ce Zhao , Yuankui Ding , Yang Zhang , Yongchao Huang , Luke Ding , Jun Liu
Abstract: A fabrication method for fabricating a thin-film transistor includes: forming a light shielding layer on a substrate; forming a buffer layer covering the light shielding layer, and forming a semiconductor material layer stacked on a surface of the buffer layer away from the substrate; forming a through hole penetrating through the buffer layer and the semiconductor material layer; patterning the semiconductor material layer to form an active layer covering a partial region of the buffer layer; forming a gate insulator layer on a surface of the active layer away from the substrate and a gate stacked on a surface of the gate insulator layer away from the substrate; forming a source and a drain on the surface of the buffer layer away from the substrate; and forming a dielectric layer covering the gate, the source, the drain, and the buffer layer, and being recessed into the through hole to form a groove.
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63.发明申请公开(公告)号：US20200091199A1
公开(公告)日：2020-03-19
申请号：US16395660
申请日：2019-04-26
Inventor： Wei Song , Ce Zhao , Bin Zhou , Dongfang Wang , Yuankui Ding , Jun Liu , Yingbin Hu , Wei Li
IPC: H01L27/12 , H01L29/786 , H01L29/66 , H01L29/40 , H01L21/3213
Abstract: A thin film transistor and a method of fabricating the same, an array substrate and a method of fabricating the same, and a display device are provided, the method of fabricating a thin film transistor includes: forming an active layer on a base substrate; forming a metal layer on the active layer; and processing the metal layer to form a source electrode, a drain electrode, and a metal oxide layer, the metal oxide layer covering the source electrode, the drain electrode, and the active layer, the source electrode and the drain electrode being spaced apart and insulated from each other by the metal oxide layer.
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公开(公告)号：US20200035767A1
公开(公告)日：2020-01-30
申请号：US16436201
申请日：2019-06-10
Inventor： Wei Song , Liangchen Yan , Ce Zhao , Dongfang Wang , Bin Zhou , Yuankui Ding , Jun Liu , Yingbin Hu , Wei Li
Abstract: The present disclosure relates to the display technology, and provides an OLED display substrate, a method for manufacturing the OLED display substrate and a display device. The method includes: forming pixel definition layer transition patterns with metal; and oxidizing the pixel definition layer transition patterns to form an insulative pixel definition layer.
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65.发明申请公开(公告)号：US20190074306A1
公开(公告)日：2019-03-07
申请号：US16037159
申请日：2018-07-17
Inventor： Jun Liu , Yongchao Huang , Tongshang Su , Leilei Cheng , Jun Wang , Ning Liu
IPC: H01L27/12 , H01L21/768 , H01L21/308 , H01L21/311 , H01L21/3213
Abstract: A method for fabricating a contact hole of an array substrate, an array substrate and a display device are disclosed, the method includes: coating a topmost layer with a first photoresist coating, exposing but not developing a part of the first photoresist coating, corresponding to a first contact hole, in an exposure process; coating the first photoresist coating with a second photoresist coating, exposing a part of the second photoresist coating, corresponding to the first contact hole, in an exposure process; developing and removing exposed parts of the first and second photoresist coatings, wherein a size of a removed part of the second photoresist coating, corresponding to the first contact hole, is smaller than a size of a removed part of the first photoresist coating, corresponding to the first contact hole; and removing parts of functional film layers, corresponding to the first contact hole, to form the first contact hole.
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Patent Agency Ranking
公开(公告)号：US20190043996A1
公开(公告)日：2019-02-07
申请号：US15991535
申请日：2018-05-29
Inventor： Jun Liu , Wei Li , Bin Zhou , Tongshang Su , Jingang Fang , Yang Zhang
IPC: H01L29/786 , H01L29/417 , H01L27/12 , G09G3/3225
Abstract: An array substrate, preparation method thereof, display panel and display device are provided. The array substrate includes a base substrate and a plurality of thin film transistors distributed on the base substrate in an array. Each thin film transistor includes: a light-shielding block formed on the base substrate and provided with a first groove of which an opening direction is away from the base substrate; a buffer layer formed on one side of the light-shielding block away from the base substrate, a region of the buffer layer corresponding to the first groove being disposed with a second groove of which an opening direction is away from the base substrate; and a channel layer formed in the second groove. The structure uses bulges on two sides of the first groove to shield the light rays in regions without the thin film transistor, thereby improving the stability of the thin film transistor.
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公开(公告)号：US10079134B2
公开(公告)日：2018-09-18
申请号：US15736278
申请日：2017-05-25
IPC: H01J37/32
CPC classification number: H01J37/321 , H01J37/32119 , H01J37/32651 , H01J2237/3344
Abstract: The present disclosure provides an inductively coupled plasma device, comprising a reaction chamber, a dielectric coupling plate, and a coil above the dielectric coupling plate. The dielectric coupling plate comprises at least two layers. The dielectric coupling plate comprises a plurality of regions, each region being provided with an electric field regulating structure, the electric field regulating structure being located between the at least two layers of the dielectric coupling plate. The electric field regulating structure is configured to regulate an intensity of an electric field that enters the reaction chamber through each region of the dielectric coupling plate.
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公开(公告)号：US12245466B2
公开(公告)日：2025-03-04
申请号：US17417334
申请日：2020-11-05
Inventor： Wei Li , Jingjing Xia , Bin Zhou , Yang Zhang , Guangyao Li , Wei Song , Xuanang Wang , Qinghe Wang , Liusong Ni , Jun Liu , Liangchen Yan , Ming Wang , Jingang Fang
IPC: H10K59/122 , H10K50/842 , H10K59/12 , H10K59/121 , H10K71/00
Abstract: The present disclosure provides an array substrate, a method for manufacturing the array substrate, a display panel and a display device. The array substrate includes: a substrate; a planarization layer on a side of the substrate; a pixel defining layer configured to define a pixel opening region and located on a side of the planarization layer away from the substrate; an anode in the pixel opening region and on a side of the planarization layer away from the substrate. The array substrate further includes an intermediate insulation layer between the planarization layer and the pixel defining layer. The intermediate insulation layer has a chemical polarity between a chemical polarity of the planarization layer and a chemical polarity of the pixel defining layer.
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公开(公告)号：US11622490B2
公开(公告)日：2023-04-04
申请号：US17346539
申请日：2021-06-14
Inventor： Wei Song , Liangchen Yan , Ce Zhao , Dongfang Wang , Bin Zhou , Yuankui Ding , Jun Liu , Yingbin Hu , Wei Li
IPC: H10K59/122 , H10K50/81 , H10K71/00 , H10K77/10 , H10K59/12 , H10K102/00
Abstract: The present disclosure relates to the display technology, and provides an OLED display substrate, a method for manufacturing the OLED display substrate and a display device. The method includes: forming pixel definition layer transition patterns with metal; and oxidizing the pixel definition layer transition patterns to form an insulative pixel definition layer.
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公开(公告)号：US20220115493A1
公开(公告)日：2022-04-14
申请号：US17329349
申请日：2021-05-25
Inventor： Yongchao Huang , Can Yuan , Liusong Ni , Chao Wang , Jiawen Song , Zhiwen Luo , Jun Liu , Leilei Cheng , Qinghe Wang , Tao Sun
Abstract: A display panel and a fabricating method thereof, and a displaying device. The display panel includes a substrate, a resistance reducing trace, an inter-layer-medium layer and a signal line. The substrate is divided into a plurality of sub-pixel regions and a pixel separating region. The resistance reducing trace is provided on the pixel separating region of the substrate. The inter-layer-medium layer is provided on the substrate, and the inter-layer-medium layer has an opening exposing the resistance reducing trace. The signal line is provided within the opening, the signal line is connected to the resistance reducing trace, the signal line is distributed in a column direction along the display panel, and in a row direction along the display panel, a width of the opening is greater than or equal to a width of the signal line.
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