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公开(公告)号：US20210384288A1
公开(公告)日：2021-12-09
申请号：US17287997
申请日：2020-08-07
Inventor： Meng LI , Yongqian LI , Zhidong YUAN , Can YUAN
IPC: H01L27/32
Abstract: A pixel structure includes: gate lines and data lines disposed crosswise and a plurality of pixel repetition modules distributed in an array. A pixel repetition module includes: a plurality of pixel units arranged in order, wherein each pixel unit includes three sub-pixels arranged in a triangular structure, and the three sub-pixels in each pixel unit and the three sub-pixels in an adjacent pixel unit are arranged inversely with respect to each other; each pixel unit corresponds to two groups of gate lines, wherein each group of gate lines includes two gate lines parallel to each other, a first group of gate lines are located on a first outer side and a second outer side of the pixel units respectively, and a second group of gate lines are both located between the sub-pixels located in a first row and the sub-pixels located in a second row in the pixel units.
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公开(公告)号：US20210335269A1
公开(公告)日：2021-10-28
申请号：US17206121
申请日：2021-03-19
Inventor： Zhidong YUAN , Pan XU , Yongqian LI , Can YUAN
IPC: G09G3/3266 , G09G3/3233 , G11C19/28
Abstract: The present disclosure relates to the field of display technology, and provides a shift register unit and a driving method thereof, a gate driving circuit, and a display panel. The shift register unit includes: an input circuit, a charging circuit, an inverter circuit, an output circuit, and a pull-down circuit. The input circuit is connected to a second clock signal terminal, a signal input terminal and a first node. The inverter circuit is connected to the signal input terminal, the second clock signal terminal, a first power supply terminal, a second power supply terminal and a pull-down node. The output circuit is connected to the pull-up node, the first power supply terminal and an output terminal. The pull-down circuit is connected to the pull-down node, the second power supply terminal, the pull-up node, and the output terminal.
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公开(公告)号：US20210225253A1
公开(公告)日：2021-07-22
申请号：US16312101
申请日：2018-01-04
Inventor： Meng LI , Yongqian LI , Zhidong YUAN , Can YUAN , Zhenfei CAI , Xuehuan FENG
IPC: G09G3/20 , G09G3/3258
Abstract: Embodiments of the present disclosure provide a shift register unit and a driving method thereof, and a gate driving circuit. The shift register unit includes an input circuit, a next-stage start circuit, a control circuit, a stabilization circuit, and at least one output circuit. The at least one output circuit each can control a voltage of a signal output terminal according to a voltage of a pull-up node, a voltage of a pull-down node, a first voltage signal, a control clock signal from a control clock signal terminal, and a control voltage signal from a control voltage signal terminal. A high level of a second clock signal begins when a high level of a first clock signal ends, and a high level of a third clock signal begins when a high level of the second clock signal ends.
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公开(公告)号：US20210217376A1
公开(公告)日：2021-07-15
申请号：US16649519
申请日：2019-03-25
Inventor： Zhidong YUAN , Yongqian LI , Haixia XU , Can YUAN
IPC: G09G3/36
Abstract: The embodiments of the present disclosure provide a shift register and a driving method thereof, a gate driving circuit, and a display device. The shift register includes a compensation selection circuit, a storage circuit, a blanking input circuit, and a shift register circuit. The compensation selection circuit is configured to provide an input signal to a first node. The storage circuit is configured to store and maintain a voltage difference between a blanking control signal terminal and the first node. The blanking input circuit is configured to provide a blanking input signal to a second node. The shift register circuit is configured to provide a compensation driving signal during a blanking period, and provide a scan driving signal during a display period.
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公开(公告)号：US20210202604A1
公开(公告)日：2021-07-01
申请号：US16977510
申请日：2019-11-29
Inventor： Zhongyuan WU , Yongqian LI , Can YUAN , Zhidong YUAN , Dacheng ZHANG , Lang LIU
IPC: H01L27/32
Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate and sub-pixels on the base substrate. At least one sub-pixel includes a storage capacitor. The storage capacitor includes a second capacitor electrode, a first capacitor electrode and a third capacitor electrode which are sequentially on the base substrate. The first capacitor electrode has a first capacitor electrode side and a second capacitor electrode side opposite to each other in the second direction, and the second capacitor electrode has a third capacitor electrode side and a fourth capacitor electrode side opposite to each other in the second direction; orthographic projections of the first capacitor electrode side and the second capacitor electrode side on the base substrate are between an orthographic projection of the third capacitor electrode side and an orthographic projection of the fourth capacitor electrode side on the base substrate.
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Patent Agency Ranking
公开(公告)号：US20210201807A1
公开(公告)日：2021-07-01
申请号：US16766450
申请日：2019-11-04
Inventor： Xuehuan FENG , Yongqian LI , Can YUAN , Meng LI , Zehua DING , Zhidong YUAN
IPC: G09G3/3266 , G09G3/3225 , G11C19/28
Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are disclosed. The shift register unit includes a first sub-unit and a leakage prevention circuit; the first sub-unit includes a first input circuit and a first output circuit. The first input circuit controls a level of a first node in response to a first input signal, the first output circuit provides an output signal at an output terminal under control of the level of the first node, the leakage prevention circuit is connected to the first node and a first voltage terminal, and controls a level of a leakage prevention node under control of the level of the first node, whereby a conductive path is formed between the leakage prevention node and the first voltage terminal, and a circuit connected between the first node and the leakage prevention node is turned off.
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67.发明申请公开(公告)号：US20210150988A1
公开(公告)日：2021-05-20
申请号：US16642469
申请日：2019-07-29
Inventor： Zhidong YUAN , Yongqian LI , Meng LI , Can YUAN
IPC: G09G3/3266 , G11C19/28
Abstract: The present disclosure discloses a shift register, a driving method thereof, a gate drive circuit, an array substrate and a display device. With a signal control circuit, a branch control circuit, a cascade signal output circuit and at least two scan signal output circuits, each shift register can output at least two scan signals to correspond to different gate lines in a display panel. This can reduce the number of shift registers in a gate drive circuit and the space occupied by the gate drive circuit and can achieve an ultra-narrow frame design, as compared with an existing shift register that can only output one scan signal. Moreover, as signals of different output control node do not influence each other, the output stability can also be improved.
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公开(公告)号：US20210125568A1
公开(公告)日：2021-04-29
申请号：US17081384
申请日：2020-10-27
Inventor： Can YUAN , Yongqian LI , Zhidong YUAN
IPC: G09G3/3291
Abstract: The present disclosure provides a display panel, a method thereof and a display device. The display panel includes a gate line group, a gate driving circuit, and a sub-pixel unit group. The sub-pixel unit group includes N rows of sub-pixel units, the gate line group includes (N+1) gate lines. The sub-pixel unit includes a light emitting unit, a pixel driving circuit, and a sensing circuit. The gate driving circuit includes output terminals, and is configured to sequentially output gate scanning signals through the output terminals. Each gate line is coupled to one corresponding output terminal. In the sub-pixel unit group, the pixel driving circuit in a sub-pixel unit in an n-th row is coupled to an n-th gate line; and the sensing circuit in the sub-pixel unit in the n-th row is coupled to a (n+1)-th gate line, where 1≤n≤N, and n is an integer.
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公开(公告)号：US20210074210A1
公开(公告)日：2021-03-11
申请号：US16840176
申请日：2020-04-03
Inventor： Zhidong YUAN , Taejin KIM , Yongqian LI , Lin SUN , Chao JIAO , Can YUAN , Zehua DING , Xuehuan FENG , Meng LI
IPC: G09G3/3233
Abstract: A pixel driving circuit, array substrate, display device and method for driving the pixel driving circuit are provided, the circuit includes: a control terminal and a first terminal of a driving switch circuit are respectively coupled to a first terminal of a data input switch circuit and an anode of a light-emitting device, and two terminals of a storage capacitor are respectively coupled to the control terminal of the driving switch circuit and the anode of the light-emitting device, two terminals of an intrinsic capacitor are respectively coupled to a cathode and the anode of the light-emitting device, a first terminal and a second terminal of a reset switch circuit are respectively coupled to the anode and the cathode of the light-emitting device, a capacitance of the intrinsic capacitor is greater than or equal to a preset multiple of a capacitance of the storage capacitor.
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公开(公告)号：US20210005127A1
公开(公告)日：2021-01-07
申请号：US17004688
申请日：2020-08-27
Inventor： Zhidong YUAN , Yongqian LI , Can YUAN
Abstract: A circuit includes an input sub-circuit configured to transmit an input signal from an input signal terminal to a feedback node under control of a first clock signal from a first clock signal terminal; a pull-up node control sub-circuit configured to transmit a feedback signal of the feedback node to a pull-up node under control of a first clock signal from the first clock signal terminal; a feedback sub-circuit configured to transmit a first voltage signal from a first voltage signal terminal to the feedback node under control of the pull-up node; an output sub-circuit configured to transmit a second clock signal from a second clock signal terminal to an output signal terminal under control of the pull-up node; and a pull-down sub-circuit configured to transmit a second voltage signal from a second voltage signal terminal to the output signal terminal under control of a pull-down node.
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