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    CONFIGURABLE LOGIC PLATFORM
    61.
    发明申请
    CONFIGURABLE LOGIC PLATFORM 审中-公开

    公开(公告)号：US20190258597A1

    公开(公告)日：2019-08-22

    申请号：US16287986

    申请日：2019-02-27

    Applicant: Amazon Technologies, Inc.

    Inventor： Islam Atta ,  Christopher Joseph Pettey ,  Asif Khan ,  Robert Michael Johnson ,  Mark Bradley Davis ,  Erez Izenberg ,  Nafea Bshara ,  Kypros Constantinides

    IPC: G06F13/40 ,  G06F15/78 ,  G06F9/445 ,  G06F13/42

    Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

    Uniform memory access architecture
    62.
    发明授权
    Uniform memory access architecture 有权

    公开(公告)号：US10346342B1

    公开(公告)日：2019-07-09

    申请号：US15451982

    申请日：2017-03-07

    Applicant: Amazon Technologies, Inc.

    Inventor： Mark Bradley Davis ,  Thomas A. Volpe ,  Nafea Bshara ,  Yaniv Shapira ,  Adi Habusha

    IPC: G06F13/42 ,  G06F13/16 ,  G06F13/40

    Abstract: A plurality of system on chips (SoCs) in a server computer can be coupled to a plurality of memory agents (MAs) via respective Serializer/Deserializer (SerDes) interfaces. Each of the plurality of MAs can include one or more memory controllers to communicate with a memory coupled to the respective MA, and globally addressable by each of the SoCs. Each of the plurality of SoCs can access the memory coupled to any of the MAs in uniform number of hops using the respective SerDes interfaces. Different types of memories, e.g., volatile memory, persistent memory, can be supported.

    Extracting debug information from FPGAs in multi-tenant environments
    63.
    发明授权
    Extracting debug information from FPGAs in multi-tenant environments 有权

    公开(公告)号：US10338135B2

    公开(公告)日：2019-07-02

    申请号：US15279276

    申请日：2016-09-28

    Applicant: Amazon Technologies, Inc.

    Inventor： Mark Bradley Davis ,  Christopher Joseph Pettey ,  Asif Khan ,  Islam Mohamed Hatem Abdulfattah Mohamed Atta

    IPC: G06F11/00 ,  G01R31/317 ,  G01R31/28 ,  G01R31/3177 ,  G06F11/36 ,  G06F9/50

    Abstract: Methods and apparatus are disclosed for programming reconfigurable logic devices such as FPGAs in a multi-tenant server environment. In one example, a computing host includes one or more processors configured to execute a supervisor process and two or more user processes and a single FPGA integrated circuit configured into a plurality of partitions. The partitions include a host logic partition that is accessible only to the supervisor process executing on the computing host, and two or more accelerator partitions. Each of the accelerator partitions is configured to include a virtual debug unit with a logic analyzer that collects logic signals generated by logic within the respective accelerator partition and sends debug data indicating values of the logic signals to one of the user processes. In some examples, the host logic partitions and/or the accelerator partitions can be independently reprogrammed of each other within their respective portions of the single FPGA.

    Presenting multiple endpoints from an enhanced PCI express endpoint device
    66.
    发明授权
    Presenting multiple endpoints from an enhanced PCI express endpoint device 有权

    公开(公告)号：US10095645B2

    公开(公告)日：2018-10-09

    申请号：US15838303

    申请日：2017-12-11

    Applicant: Amazon Technologies, Inc.

    Inventor： Mark Bradley Davis ,  Anthony Nicholas Liguori

    IPC: G06F9/455 ,  G06F13/38 ,  G06F13/10

    Abstract: A system that provides virtualized computing resources to clients or subscribers may include an enhanced PCIe endpoint device on which an emulation processor emulates PCIe compliant hardware devices in software. In response to receiving a transaction layer packet that includes a transaction directed to an emulated device, the endpoint device may process the transaction, which may include emulating the target emulated device. The endpoint device may include multiple PCIe controllers and may expose multiple PCIe endpoints to a host computing system. For example, each PCIe controller may be physically coupled to one of multiple host processor sockets or host server SOCs on the host computing system, each of which exposes its own root complex. Traffic received by the PCIe controllers may be merged on the endpoint device for subsequent processing. Traffic originating at one host processor socket may be steered to the PCIe controller to which it is directly attached.

    Systems and methods for I/O device logging
    67.
    发明授权
    Systems and methods for I/O device logging 有权

    公开(公告)号：US10067741B1

    公开(公告)日：2018-09-04

    申请号：US14562556

    申请日：2014-12-05

    Applicant: Amazon Technologies, Inc.

    Inventor： Asif Khan ,  Mark Bradley Davis ,  Anthony Nicholas Liguori ,  David James Borland

    IPC: G06F3/00 ,  G06F5/00 ,  G06F13/00 ,  G06F13/36 ,  G06F5/08 ,  G06F5/14 ,  H04J3/14 ,  H04L12/861

    Abstract: Techniques are described for logging communication traffic associated with one or more devices. For example, a system bus or other interface to a device may be monitored for traffic data elements. The traffic data elements may include, for example, transaction layer packets (TLPs) for communication across a PCI Express interface, or Ethernet packets for communication over a network. The traffic data elements can be processed by a classifier module and accordingly routed to one of a plurality of circular buffers. The circular buffers may maintain state (e.g., a head pointer and a tail pointer) that identify traffic data elements that are pending and those that are completed. Thus, the circular buffers can be inspected (such as after a crash) to determine recent activity.

    Streaming interconnect architecture
    68.
    发明授权
    Streaming interconnect architecture 有权

    公开(公告)号：US09940284B1

    公开(公告)日：2018-04-10

    申请号：US14673474

    申请日：2015-03-30

    Applicant: Amazon Technologies, Inc.

    Inventor： Mark Bradley Davis ,  Asif Khan ,  Thomas A. Volpe ,  Robert Michael Johnson

    IPC: G06F13/40 ,  G06F13/42

    CPC classification number: G06F13/4027 ,  G06F13/4221

    Abstract: A device can include one of more configurable packet processing pipelines to process a plurality of packets. Each configurable packet processing pipeline can include a plurality of packet processing components, wherein each packet processing component is configured to perform one or more packet processing operations for the device. The plurality of packet processing components are coupled to a packet processing interconnect, wherein each packet processing component is configured to route the packets through the packet processing interconnect for the one or more configurable packet processing pipelines.

    Single function using multiple ports
    70.
    发明授权
    Single function using multiple ports 有权

    公开(公告)号：US09910813B1

    公开(公告)日：2018-03-06

    申请号：US14614356

    申请日：2015-02-04

    Applicant: Amazon Technologies, Inc.

    Inventor： Asif Khan ,  Mark Bradley Davis

    IPC: G06F13/20 ,  G06F13/42 ,  G06F13/40 ,  G06F13/38

    CPC classification number: G06F13/4221 ,  G06F13/385 ,  G06F13/4022

    Abstract: An electronics adapter, system, and methods for using multiple interface ports to execute a single function are disclosed herein. The electronics adapter may include multiple interface ports, each having a transmission capacity for data transmitted via each interface port. Processing logic may be coupled to the two or more interface ports, to execute processes associated with the multiple interface ports utilizing a bandwidth. The electronics adapter may further include a controller to configure and merge the data from the multiple interface ports based at least in part on the transmission capacities for the multiple interface ports to support the bandwidth of the processes.

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