公开(公告)号：US07579255B2

公开(公告)日：2009-08-25

申请号：US10879757

申请日：2004-06-30

申请人： Seung-Ho Pyi

发明人： Seung-Ho Pyi

IPC分类号： H01L21/76

CPC分类号： H01L21/76232 ,  H01L21/764 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to a semiconductor device and a method for isolating the same. The semiconductor device includes: a silicon substrate provided with a trench including at least one silicon pillar at a bottom portion of the trench, wherein the silicon pillar become sidewalls of micro trenches; and a device isolation layer selectively and partially filled into the plurality of micro trenches.

摘要翻译： 本发明涉及半导体器件及其分离方法。 半导体器件包括：硅衬底，其设置有在沟槽的底部具有至少一个硅柱的沟槽，其中硅柱变成微沟槽的侧壁; 以及选择性地和部分地填充到多个微沟槽中的器件隔离层。

公开(公告)号：US20090004802A1

公开(公告)日：2009-01-01

申请号：US11966231

申请日：2007-12-28

申请人： Moon Sig Joo ,  Seung Ho Pyi ,  Ki Seon Park ,  Heung Jae Cho ,  Yong Top Kim

发明人： Moon Sig Joo ,  Seung Ho Pyi ,  Ki Seon Park ,  Heung Jae Cho ,  Yong Top Kim

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/115 ,  Y10S438/942

摘要： A method of fabricating a non-volatile memory device having a charge trapping layer includes forming a tunneling layer, a charge trapping layer, a blocking layer and a control gate electrode layer over a substrate, forming a mask layer pattern on the control gate electrode layer, performing an etching process using the mask layer pattern as an etching mask to remove an exposed portion of the control gate electrode layer, wherein the etching process is performed as excessive etching to remove the charge trapping layer by a specified thickness, forming an insulating layer for blocking charges from moving on the control gate electrode layer and the mask layer pattern, performing anisotropic etching on the insulating layer to form an insulating layer pattern on a sidewall of the control gate electrode layer and a partial upper sidewall of the blocking layer, and performing an etching process on the blocking layer exposed by the anisotropic etching, wherein the etching process is performed as excessive etching to remove the charge trapping layer by a specified thickness.

摘要翻译： 一种制造具有电荷捕获层的非易失性存储器件的方法包括在衬底上形成隧道层，电荷俘获层，阻挡层和控制栅电极层，在控制栅电极层上形成掩模层图案 使用掩模层图案作为蚀刻掩模进行蚀刻处理以去除控制栅电极层的暴露部分，其中蚀刻工艺作为过度蚀刻进行，以将电荷捕获层除去指定厚度，形成绝缘层 用于阻止电荷在控制栅电极层和掩模层图案上移动，对绝缘层进行各向异性蚀刻，以在控制栅电极层的侧壁和阻挡层的一部分上侧壁上形成绝缘层图案，以及 对通过各向异性蚀刻暴露的阻挡层进行蚀刻处理，其中执行蚀刻处理 作为过量蚀刻以将电荷捕获层除去指定的厚度。

公开(公告)号：US07214584B2

公开(公告)日：2007-05-08

申请号：US11149297

申请日：2005-06-10

申请人： Seung-Ho Pyi

发明人： Seung-Ho Pyi

IPC分类号： H01L21/8242

CPC分类号： H01L28/91 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L27/10814 ,  H01L27/10855

摘要： Disclosed is a method for preventing a bunker defect generation on a lower portion of a cylinder type metal bottom electrode. The method includes the steps of: forming an etch stop layer on a bottom structure with a conductive region and an insulation region; forming a capacitor insulation layer on the etch stop layer; forming an opening exposing the conductive region by selectively etching the capacitor insulation layer and the etch stop layer; growing a selective epitaxial growth (SEG) layer in the conductive region exposed through the opening; forming a metal layer for a capacitor bottom electrode along a profile provided with the opening; forming an isolated capacitor bottom electrode by removing the metal layer until the capacitor insulation layer is exposed; and removing the capacitor insulation layer, thereby making the capacitor bottom electrode have a cylinder type structure.

摘要翻译： 公开了一种用于防止在气缸型金属底部电极的下部产生掩体缺陷的方法。 该方法包括以下步骤：在具有导电区域和绝缘区域的底部结构上形成蚀刻停止层; 在所述蚀刻停止层上形成电容器绝缘层; 通过选择性地蚀刻电容器绝缘层和蚀刻停止层，形成露出导电区域的开口; 在通过开口暴露的导电区域中生长选择性外延生长（SEG）层; 沿着设置有所述开口的轮廓形成用于电容器底部电极的金属层; 通过去除金属层形成隔离电容器底部电极，直到电容器绝缘层暴露; 并且去除电容器绝缘层，从而使电容器底部电极具有圆筒型结构。

公开(公告)号：US20050139951A1

公开(公告)日：2005-06-30

申请号：US10879757

申请日：2004-06-30

申请人： Seung-Ho Pyi

发明人： Seung-Ho Pyi

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/764 ,  H01L29/00

CPC分类号： H01L21/76232 ,  H01L21/764 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to a semiconductor device and a method for isolating the same. The semiconductor device includes: a silicon substrate provided with a trench including at least one silicon pillar at a bottom portion of the trench, wherein the silicon pillar become sidewalls of micro trenches; and a device isolation layer selectively and partially filled into the plurality of micro trenches.

摘要翻译： 本发明涉及半导体器件及其分离方法。 半导体器件包括：硅衬底，其设置有在沟槽的底部具有至少一个硅柱的沟槽，其中硅柱变成微沟槽的侧壁; 以及选择性地和部分地填充到多个微沟槽中的器件隔离层。